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Commit ddc67a76 authored by Silviu Baranga's avatar Silviu Baranga
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Added the missing bit definition for the 4th bit of the STR (post reg)... 

Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.

llvm-svn: 156609
parent 5a719f9b
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