[AArch64][CodeGen] Always use SVE (when enabled) to lower 64-bit vector multiplies
This patch adds custom lowering support for ISD::MUL with v1i64 and v2i64 types when SVE is enabled, regardless of the minimum SVE vector length. We do this because NEON simply does not have 64-bit vector multiplies, so we want to take advantage of these instructions in SVE. I've updated the 128-bit min SVE vector bits tests here: CodeGen/AArch64/sve-fixed-length-int-arith.ll CodeGen/AArch64/sve-fixed-length-int-mulh.ll CodeGen/AArch64/sve-fixed-length-int-rem.ll Differential Revision: https://reviews.llvm.org/D118802
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