Commits · 03aa963077b93623efe8adf235847858a61eab04 · Lorenzo Albano / LLVM bpEVL · GitLab

Jul 01, 2011
- Rename TargetSubtarget to TargetSubtargetInfo for consistency. · 0d639a28
  Evan Cheng authored Jul 01, 2011
  0d639a28
Jun 29, 2011
- Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC. · 8264e272
  Evan Cheng authored Jun 29, 2011
  8264e272
Jun 28, 2011
- - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and · 6cc775f9
  Evan Cheng authored Jun 28, 2011
  6cc775f9
Jun 02, 2011
- Remove dead code. · 5ca08373
  Devang Patel authored Jun 02, 2011
  5ca08373
- Update DBG_VALUEs while breaking anti dependencies. · f02a376f
  Devang Patel authored Jun 02, 2011
  f02a376f
- During post RA scheduling, do not try to chase reg defs. to preserve... · e5feef0f
  Devang Patel authored Jun 02, 2011
  e5feef0f
May 06, 2011
- Added an assertion, and updated a comment. · 2e116a44
  Andrew Trick authored May 06, 2011
  2e116a44
May 05, 2011
- ARM post RA scheduler compile time fix. · 3dc73aae
  Andrew Trick authored May 05, 2011
  3dc73aae
- whitespace · 24b1c485
  Andrew Trick authored May 05, 2011
  24b1c485
Apr 15, 2011
- Fix a ton of comment typos found by codespell. Patch by · 0ab5e2cd
  Chris Lattner authored Apr 15, 2011
  0ab5e2cd
Jan 08, 2011
- Do not model all INLINEASM instructions as having unmodelled side effects. · 6eb516db
  Evan Cheng authored Jan 07, 2011
  6eb516db
Dec 15, 2010
- Move Value::getUnderlyingObject to be a standalone · a4fcd241
  Dan Gohman authored Dec 15, 2010
  a4fcd241
Nov 03, 2010
- Two sets of changes. Sorry they are intermingled. · debf9c50
  Evan Cheng authored Nov 03, 2010
  debf9c50
Oct 28, 2010
- Putting r117193 back except for the compile time cost. Rather than assuming... · cbdf7e87
  Evan Cheng authored Oct 27, 2010
  cbdf7e87
Oct 26, 2010
- Neuter r117193 as it causes significant post-ra scheduler compile time regression. · 43d6f34e
  Evan Cheng authored Oct 25, 2010
  43d6f34e
Oct 23, 2010
- Properly model the latency of register defs which are 1) function returns or · 15459b69
  Evan Cheng authored Oct 23, 2010
  15459b69
Oct 09, 2010
- Avoid compiler warning: comparison between signed and unsigned integer. · df2aae0c
  Evan Cheng authored Oct 08, 2010
  df2aae0c
Oct 08, 2010
- Fix operand latency computation in cases where the definition operand is · 8c5e7e51
  Evan Cheng authored Oct 08, 2010
  8c5e7e51
Oct 06, 2010
- Remove unused variables. · ec0da969
  Nick Lewycky authored Oct 06, 2010
  ec0da969
- - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This · 49d4c0bd
  Evan Cheng authored Oct 06, 2010
  49d4c0bd
Sep 30, 2010
- Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP · 4a010fd1
  Evan Cheng authored Sep 29, 2010
  4a010fd1
Sep 10, 2010
- Teach if-converter to be more careful with predicating instructions that would · bf407075
  Evan Cheng authored Sep 10, 2010
  bf407075
Jul 24, 2010
- Change ScheduleDAGInstrs::Defs and ::Uses to be variable-size vectors · 56c00656
  Bob Wilson authored Jul 24, 2010
  56c00656
Jul 15, 2010
- Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. · 2da75ef3
  Bill Wendling authored Jul 15, 2010
  2da75ef3
May 20, 2010
- Fix the post-RA instruction scheduler to handle instructions referenced by · 604560c5
  Jim Grosbach authored May 19, 2010
  604560c5
May 01, 2010
- Get rid of the EdgeMapping map. Instead, just check for BasicBlock · 25c16537
  Dan Gohman authored May 01, 2010
  25c16537
Apr 17, 2010
- Fix -Wcast-qual warnings. · 1f0f2142
  Dan Gohman authored Apr 17, 2010
  1f0f2142
Mar 22, 2010
- Reduce indentation. · 14694d36
  Evan Cheng authored Mar 22, 2010
  14694d36
- 80 col violation. · 760dc65d
  Evan Cheng authored Mar 22, 2010
  760dc65d
Mar 10, 2010
- Progress towards shepherding debug info through SelectionDAG. · 49de0607
  Dale Johannesen authored Mar 10, 2010
  49de0607
Feb 16, 2010
- There are two ways of checking for a given type, for example isa<PointerType>(T) · 19d0b47b
  Duncan Sands authored Feb 16, 2010
  19d0b47b
Nov 09, 2009
- Fix dependencies added to model memory aliasing for post-RA scheduling. The... · d2f9c044
  David Goodwin authored Nov 09, 2009
  d2f9c044
Nov 05, 2009
- Correctly add chain dependencies around calls and unknown-side-effect instructions. · 28ba4f27
  David Goodwin authored Nov 05, 2009
  28ba4f27
Nov 03, 2009
- <rdar://problem/7352605 >. When building schedule graph use mayAlias... · a86f9197
  David Goodwin authored Nov 03, 2009
  a86f9197
Nov 02, 2009
- Chain dependencies used to enforce memory order should have latency of 0... · 00822aab
  David Goodwin authored Nov 02, 2009
  00822aab
Oct 26, 2009
- When checking whether a def of an aliased register is dead, ask the · 9aba0d99
  Dan Gohman authored Oct 26, 2009
  9aba0d99
Oct 18, 2009
- Spill slots cannot alias. · f0236e01
  Evan Cheng authored Oct 18, 2009
  f0236e01
- -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed · 0e9d9ca8
  Evan Cheng authored Oct 18, 2009
  0e9d9ca8
Oct 10, 2009
- Factor out LiveIntervalAnalysis' code to determine whether an instruction · 87b02d5b
  Dan Gohman authored Oct 09, 2009
  87b02d5b
Oct 07, 2009
- Replace TargetInstrInfo::isInvariantLoad and its target-specific · be8137b0
  Dan Gohman authored Oct 07, 2009
  be8137b0