- Add AVX SSE2 Move doubleword and quadword instructions.
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365

llvm-svn: 107308

llvm-svn: 107306

llvm-svn: 107300

llvm-svn: 107293

llvm-svn: 107280

llvm-svn: 107246

llvm-svn: 107245

llvm-svn: 107243

llvm-svn: 107241

llvm-svn: 107240

- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238

llvm-svn: 107225

llvm-svn: 107215

llvm-svn: 107213

llvm-svn: 107211

llvm-svn: 107206

metadata types which should be marked as "weak", but which the linker will
remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is
defined like this:

       .globl l_objc_msgSend_fixup_alloc
       .weak_definition l_objc_msgSend_fixup_alloc
       .section __DATA, __objc_msgrefs, coalesced
       .align 3
l_objc_msgSend_fixup_alloc:
        .quad   _objc_msgSend_fixup
        .quad   L_OBJC_METH_VAR_NAME_1

This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".

llvm-svn: 107205

Add AVX ld/st XCSR register.
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204

llvm-svn: 107201

llvm-svn: 107178

llvm-svn: 107168

The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.

llvm-svn: 107167

llvm-svn: 107166

llvm-svn: 107154

a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.

llvm-svn: 107147

of getPhysicalRegisterRegClass with it.

If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.

llvm-svn: 107140

llvm-svn: 107135

and thumb_mode.

llvm-svn: 107133

llvm-svn: 107131

llvm-svn: 107130

llvm-svn: 107127

llvm-svn: 107122

llvm-svn: 107121

llvm-svn: 107116

llvm-svn: 107114

llvm-svn: 107108

the same as ARM except that the condition code field is always set to ARMCC::AL.

llvm-svn: 107107

of the Subtarget.

llvm-svn: 107086

llvm-svn: 107073