getShiftAmountTy (i32 in the case of CellSPU).

llvm-svn: 58449

llvm-svn: 58443

llvm-svn: 58433

One will only see an effect if legalizetype is not active.  Will move
support to LegalizeType soon.

llvm-svn: 58426

so that va_start/va_arg/et.al. will walk arguments correctly for Cell SPU.

N.B.: Because neither clang nor llvm-gcc-4.2 can be built for CellSPU, this is
still unexorcised code.

llvm-svn: 58415

llvm-svn: 58409

llvm-svn: 58408

llvm-svn: 58407

llvm-svn: 58403

allows ppcf128->int conversion to work with
DeadInstructionElimination.  This is now turned
off but RM is harmless.  It does not do a complete
job of modeling the rounding mode.

Revert marking MFCR as using all 7 CR subregisters;
while correct, this caused the problem in PR 2964,
plus the local RA crash noted in the comments.
This was needed to make DeadInstructionElimination,
but as we are not running that, it is backed out
for now.  Eventually it should go back in and the
other problems fixed where they're broken.

llvm-svn: 58391

llvm-svn: 58386

I don't really see this as being needed, but there is little harm from doing
it.

llvm-svn: 58385

VAARG.

llvm-svn: 58379

other day that PPC custom lowering could create
a BUILD_PAIR of two f64 with a result type of...
f64! - already fixed).  Fix a place that triggers
the sanity check.

llvm-svn: 58378

- If a def is spilt, remember its spill index to allow its reuse.

llvm-svn: 58375

is morphed by AnalyzeNewNode into a previously
processed node, and different result values of
that node are remapped to values with different
nodes, then we could end up using wrong values
here [we were assuming that all results remap
to values with the same underlying node].  This
seems theoretically possible, but I don't have
a testcase.  The meat of the patch is in the
changes to AnalyzeNewNode/AnalyzeNewValue and
ReplaceNodeWith.  While there, I changed names
like RemapNode to RemapValue, since it really
remaps values.  To tell the truth, I would be
much happier if we were only remapping nodes
(it would simplify a bunch of logic, and allow
for some cute speedups) but I haven't yet worked
out how to do that.

llvm-svn: 58372

llvm-svn: 58371

llvm-svn: 58370

- Create and update spill slot live intervals.
- Lots of bug fixes.

llvm-svn: 58367

 - No functionality change.

llvm-svn: 58355

 - No functionality change.

llvm-svn: 58352

llvm-svn: 58351

EnableFastISelAbort variables for Release mode instead of
using ifdefs in the code.

llvm-svn: 58350

 - One functionality change, '\\' in a name is now printed as a hex
   escape instead of "\\\\". This is consistent with other users of
   PrintEscapedString.

llvm-svn: 58343

llvm-svn: 58340

Since the ARM constant pool handling supercedes the standard LLVM constant
pool entirely, the JIT emitter does not allocate space for the constants,
nor initialize the memory. The constant pool is considered part of the 
instruction stream.

Likewise, when resolving relocations into the constant pool, a hook into
the target back end is used to resolve from the constant ID# to the
address where the constant is stored.

For now, the support in the ARM emitter is limited to 32-bit integer. Future
patches will expand this to the full range of constants necessary.

llvm-svn: 58338

ppcf128 to i32 conversion and expand it into a code
sequence like in LegalizeDAG.  This needs custom
ppc lowering of FP_ROUND_INREG, so turn that on and
make it work with LegalizeTypes.  Probably PPC should
simply custom lower the original conversion.

llvm-svn: 58329

id could end up being wrong mostly because of
forgetting to remap new nodes that morphed into
processed nodes through CSE.

llvm-svn: 58323

llvm-svn: 58320

llvm-svn: 58319

a memset using 16-byte XMM stores, but where the stack realignment code
didn't work.  Until it does (PR2962) disable use of xmm regs in memcpy
and memset formation for linux and other targets with insufficiently
aligned stacks.

This is part of PR2888

llvm-svn: 58317

llvm-svn: 58314

llvm-svn: 58312

Avoid putting a split past the end of the live range; always shrink wrap live interval in the barrier mbb.

llvm-svn: 58309

llvm-svn: 58297

Re-apply 55137 with fixes.

llvm-svn: 58296

llvm-svn: 58294

llvm-svn: 58290

Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag.  Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like.  This really helps when debugging instruction selection.

llvm-svn: 58278

Add setSubgraphColor to color an entire portion of a SelectionDAG.  This
will be used to support debug features in TableGen.

llvm-svn: 58257