llvm-svn: 105488

class object in blocks and carry it to IRGen.

llvm-svn: 105487

llvm-svn: 105485

llvm-svn: 105484

llvm-svn: 105481

llvm-svn: 105480

No functionality change yet.

llvm-svn: 105479

was given.  Remove some unnecessary accounting from BlockScopeInfo.  Handle
typedef'ed function types until such time as we decide not.

llvm-svn: 105478

arguments after translation, instead of the -cc1 level arguments.

llvm-svn: 105476

added as the last output step, instead of just hacking it into the link step.
 - Among other things, this fixes dSYM generation when using multiple -arch options.

llvm-svn: 105475

llvm-svn: 105474

register allocation.

Process all of the clobber lists at the end of the function, marking the
registers as used in MachineRegisterInfo.

This is necessary in case the calls clobber callee-saved registers (sic).

llvm-svn: 105473

8060143, although this doesn't fix the real problem with tail call.

llvm-svn: 105472

llvm-svn: 105470

setting up block's descriptor. This is on going work to
support c++ specific issues in setting up blocks
various APIs.

llvm-svn: 105469

moves us further.

llvm-svn: 105468

llvm-svn: 105467

the case where we pick up block arguments from a typedef.  Save the block
signature as it was written, and preserve same through PCH.

llvm-svn: 105466

llvm-svn: 105465

type parameter pack is distinct from a template type parameter.

llvm-svn: 105464

Allows this check to work properly for instantiated fields and removes
an unnecessary GetTypeForDeclarator call.

llvm-svn: 105463

type-parameter within a template parameter list. Found by inspection. 

llvm-svn: 105462

llvm-svn: 105461

llvm-svn: 105458

llvm-svn: 105457

llvm-svn: 105456

llvm-svn: 105454

replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE
when recursively updating nodes.  Since OpA has been processed, the new uses are
not examined again.  The patch checks if this occurred and it it did, updates the
new uses of OpA to use OpB.

llvm-svn: 105453

llvm-svn: 105452

Fixed Objective-C type encoding for bitfields for the GNU runtime to match the encoding used by GCC.

llvm-svn: 105451

llvm-svn: 105450

functions where they belong.

llvm-svn: 105449

llvm-svn: 105448

Use CXXRecordDecl::getFinalOverriders to get final overriders. This speeds up vtable layout by moving away from the old final overrider computation code that had O(N^2) complexity in some cases.

llvm-svn: 105447

llvm-svn: 105445

Add skeleton of support for emitting the list of prototypes for BuiltinsARM.def

llvm-svn: 105443

llvm-svn: 105442

llvm-svn: 105441

llvm-svn: 105440

VECTOR_SHUFFLEs to REG_SEQUENCE instructions.  The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized.  That is pretty awful, but I guess it
makes sense for other targets.  Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.

llvm-svn: 105439