llvm-svn: 243999

llvm-svn: 159864

A MOVCCr instruction can be commuted by inverting the condition. This
can help reduce register pressure and remove unnecessary copies in some
cases.

<rdar://problem/11182914>

llvm-svn: 154033

(and other targets).

llvm-svn: 149182

llvm-svn: 135024

llvm-svn: 126930

llvm-svn: 109458

llvm-svn: 109456

llvm-svn: 109448

instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.

llvm-svn: 108608

llvm-svn: 108396

llvm-svn: 108328

llvm-svn: 99815

llvm-svn: 96490

llvm-svn: 95609

cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.

llvm-svn: 94119

llvm-svn: 86494

llvm-svn: 86330

llvm-svn: 85798

llvm-svn: 85797

llvm-svn: 85624

instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982

llvm-svn: 77598

Disable my constant island pass optimization (to make use soimm more effectively). It caused infinite looping on lencod.

llvm-svn: 76995

llvm-svn: 76711

After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420

llvm-svn: 74241

llvm-svn: 74239

This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919

llvm-svn: 44382

llvm-svn: 44380

llvm-svn: 43164

llvm-svn: 41808

llvm-svn: 38513

llvm-svn: 36586

llvm-svn: 36273

llvm-svn: 36203

llvm-svn: 35229

llvm-svn: 35049

llvm-svn: 35048