- Jul 13, 2011
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Evan Cheng authored
if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 llvm-svn: 135017
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- Jul 12, 2011
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Jay Foad authored
StructType::get() and TargetData::getIntPtrType(). llvm-svn: 134982
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Bill Wendling authored
an assert on Darwin llvm-gcc builds. Assertion failed: (castIsValid(op, S, Ty) && "Invalid cast!"), function Create, file /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.llvm-gcc-i386-darwin9-RA/llvm.src/lib/VMCore/Instructions.cpp, li\ ne 2067. etc. http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA/builds/2354 --- Reverse-merging r134893 into '.': U include/llvm/Target/TargetData.h U include/llvm/DerivedTypes.h U tools/bugpoint/ExtractFunction.cpp U unittests/Support/TypeBuilderTest.cpp U lib/Target/ARM/ARMGlobalMerge.cpp U lib/Target/TargetData.cpp U lib/VMCore/Constants.cpp U lib/VMCore/Type.cpp U lib/VMCore/Core.cpp U lib/Transforms/Utils/CodeExtractor.cpp U lib/Transforms/Instrumentation/ProfilingUtils.cpp U lib/Transforms/IPO/DeadArgumentElimination.cpp U lib/CodeGen/SjLjEHPrepare.cpp --- Reverse-merging r134888 into '.': G include/llvm/DerivedTypes.h U include/llvm/Support/TypeBuilder.h U include/llvm/Intrinsics.h U unittests/Analysis/ScalarEvolutionTest.cpp U unittests/ExecutionEngine/JIT/JITTest.cpp U unittests/ExecutionEngine/JIT/JITMemoryManagerTest.cpp U unittests/VMCore/PassManagerTest.cpp G unittests/Support/TypeBuilderTest.cpp U lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp U lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp U lib/VMCore/IRBuilder.cpp G lib/VMCore/Type.cpp U lib/VMCore/Function.cpp G lib/VMCore/Core.cpp U lib/VMCore/Module.cpp U lib/AsmParser/LLParser.cpp U lib/Transforms/Utils/CloneFunction.cpp G lib/Transforms/Utils/CodeExtractor.cpp U lib/Transforms/Utils/InlineFunction.cpp U lib/Transforms/Instrumentation/GCOVProfiling.cpp U lib/Transforms/Scalar/ObjCARC.cpp U lib/Transforms/Scalar/SimplifyLibCalls.cpp U lib/Transforms/Scalar/MemCpyOptimizer.cpp G lib/Transforms/IPO/DeadArgumentElimination.cpp U lib/Transforms/IPO/ArgumentPromotion.cpp U lib/Transforms/InstCombine/InstCombineCompares.cpp U lib/Transforms/InstCombine/InstCombineAndOrXor.cpp U lib/Transforms/InstCombine/InstCombineCalls.cpp U lib/CodeGen/DwarfEHPrepare.cpp U lib/CodeGen/IntrinsicLowering.cpp U lib/Bitcode/Reader/BitcodeReader.cpp llvm-svn: 134949
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- Jul 11, 2011
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Evan Cheng authored
llvm-svn: 134922
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Jim Grosbach authored
The 'CS' is not a predication suffix in this case. llvm-svn: 134903
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Jim Grosbach authored
Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902
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Jay Foad authored
llvm-svn: 134893
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Evan Cheng authored
and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
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- Jul 10, 2011
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Jakub Staszak authored
llvm-svn: 134858
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- Jul 09, 2011
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Evan Cheng authored
CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. llvm-svn: 134795
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Evan Cheng authored
llvm-svn: 134764
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Evan Cheng authored
llvm-svn: 134760
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Jim Grosbach authored
llvm-svn: 134758
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Jim Grosbach authored
llvm-svn: 134755
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- Jul 08, 2011
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Jim Grosbach authored
The normal tBX instruction is predicable, so there's no reason the pseudos for using it as a return shouldn't be. Gives us some nice code-gen improvements as can be seen by the test changes. In particular, several tests now have to disable if-conversion because it works too well and defeats the test. llvm-svn: 134746
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Cameron Zwarich authored
is to use this for architectures that have a native FMA instruction. llvm-svn: 134742
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Jim Grosbach authored
llvm-svn: 134739
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Benjamin Kramer authored
Found by valgrind. llvm-svn: 134738
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Jim Grosbach authored
No functional change. llvm-svn: 134737
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Jim Grosbach authored
llvm-svn: 134734
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Jim Grosbach authored
llvm-svn: 134732
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Jim Grosbach authored
llvm-svn: 134729
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Jim Grosbach authored
Fix a FIXME. llvm-svn: 134727
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Evan Cheng authored
llvm-svn: 134721
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Jim Grosbach authored
llvm-svn: 134719
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Jim Grosbach authored
No functional change. llvm-svn: 134714
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Jim Grosbach authored
TableGen'erated MC lowering pseudo-expansion. llvm-svn: 134712
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Chandler Carruth authored
llvm-svn: 134707
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Jim Grosbach authored
Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
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Evan Cheng authored
- Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
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- Jul 07, 2011
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Evan Cheng authored
llvm-svn: 134627
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Evan Cheng authored
llvm-svn: 134626
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Oscar Fuentes authored
llvm-svn: 134616
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Douglas Gregor authored
llvm-svn: 134614
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Cameron Zwarich authored
multiply-accumulate instructions with separate rounding steps. llvm-svn: 134609
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Evan Cheng authored
llvm-svn: 134608
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Evan Cheng authored
llvm-svn: 134606
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Evan Cheng authored
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590
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Evan Cheng authored
Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC. llvm-svn: 134569
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