Commits · 16af97393346ad636298605930a8b503a55eb40a · Lorenzo Albano / LLVM bpEVL · GitLab

Feb 16, 2021
- [MC][ELF] Support for zero flag section groups · 16af9739
  Petr Hosek authored Jan 31, 2021
  16af9739
- [NFC][PPC] Refactor TOC representation to allow several entries for the same symbol · de3a485d
  Victor Huang authored Feb 16, 2021
  de3a485d
- Revert "[DAG] Fold shuffle(bop(shuffle(x,y),shuffle(z,w)),bop(shuffle(a,b),shuffle(c,d)))" · 5aa8f4c0
  Sterling Augustine authored Feb 16, 2021
  5aa8f4c0
- [RISCV] Add isel patterns for fixed vector fmsub/fnmadd/fnmsub. · 61a238e6
  Craig Topper authored Feb 16, 2021
  
  61a238e6
- Revert "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE" · 962b73dd
  Jessica Paquette authored Feb 16, 2021
  962b73dd
- [RISCV] Add support for fixed vector mask logic operations. · 07ca13fe
  Craig Topper authored Feb 16, 2021
  07ca13fe
- [AArch64] Convert CMP/SELECT sign patterns to OR & ASR. · 211147c5
  Florian Hahn authored Feb 16, 2021
  211147c5
- [ARM] Use rGPR for writeback vldrs · 1e007cf4
  David Green authored Feb 16, 2021
  1e007cf4
- AMDGPU: Remove kills following clusters of memory instruction · a7455d7b
  Matt Arsenault authored Feb 14, 2021
  a7455d7b
- [DAG] Fold shuffle(bop(shuffle(x,y),shuffle(z,w)),bop(shuffle(a,b),shuffle(c,d))) · 5dfba562
  Simon Pilgrim authored Feb 16, 2021
  5dfba562
- AMDGPU: Fix debug info handling in post-RA bundler · c320e819
  Matt Arsenault authored Feb 14, 2021
  c320e819
- [llvm][Aarch64][SVE] Remove extra fmov instruction with certain literals · e86f9ba1
  David Truby authored Feb 16, 2021
  e86f9ba1
- [SVE] Add support for scalable vectorization of loops with int/fast FP reductions · ba1e150d
  Kerry McLaughlin authored Feb 16, 2021
  ba1e150d
- [RISCV] Fix a crash in fixed-length build_vector lowering · 04977ce5
  Fraser Cormack authored Feb 15, 2021
  04977ce5
- [RISCV] Add patterns for scalable-vector fabs & fcopysign · b8701990
  Fraser Cormack authored Feb 04, 2021
  b8701990
Feb 15, 2021
- [RISCV] Add expicit i32/i64 types to RV32 or RV64 only isel patterns. NFC · 29b894a8
  Craig Topper authored Feb 15, 2021
  29b894a8
- GlobalISel: Handle arguments partially passed on the stack · 392e0fcf
  Matt Arsenault authored Feb 07, 2021
  392e0fcf
- [RISCV] Add support for fixed vector floating point setcc. · 7ba2e1c6
  Craig Topper authored Feb 15, 2021
  7ba2e1c6
- TransformUtils: Fix metadata handling in CloneModule (and improve CloneFunctionInto) · 22a52dfd
  Duncan P. N. Exon Smith authored Feb 11, 2021
  22a52dfd
- [AMDGPU] Add two TSFlags: IsAtomicNoRtn and IsAtomicRtn · 5cf9292c
  Stanislav Mekhanoshin authored Feb 12, 2021
  5cf9292c
- [AArch64] Move machine bundle unpacking to PreEmit2 phase. · ca23b2c8
  Florian Hahn authored Feb 15, 2021
  ca23b2c8
- [ARM] Add some basic Min/Max costs · 0a98efb0
  David Green authored Feb 15, 2021
  0a98efb0
- [CostModel]Add cost model for experimental.vector.reverse · b52e6c58
  Caroline Concatto authored Jan 27, 2021
  b52e6c58
- [CodeGen][SelectionDAG]Add new intrinsic experimental.vector.reverse · 2d728bbf
  Caroline Concatto authored Jan 15, 2021
  2d728bbf
- [ARM] Extend search for increment in load/store optimizer · a838a4f6
  David Green authored Feb 15, 2021
  a838a4f6
- Recommit "[TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode" · 357237e9
  Sjoerd Meijer authored Feb 15, 2021
  357237e9
- Revert "[TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode" · effc3b07
  Sjoerd Meijer authored Feb 15, 2021
  effc3b07
- [TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode · cd6de0e8
  Sjoerd Meijer authored Feb 12, 2021
  cd6de0e8
- [RISCV] Convert VSLIDE(UP|DOWN) nodes to "VL" versions (NFC) · 4bd5bd40
  Fraser Cormack authored Feb 11, 2021
  4bd5bd40
- Add ehcont section support · 08086647
  Arlo Siemsen authored Feb 15, 2021
  08086647
- [AMDGPU] Add llvm.amdgcn.wqm.demote intrinsic · aef781b4
  Carl Ritson authored Feb 14, 2021
  aef781b4
Feb 14, 2021
- [AMDGPU] Limit memory scope for scratch, LDS and GDS · 8a91b68b
  Tony Tye authored Feb 13, 2021
  8a91b68b
- [AMDGPU] Fix build breakage · b4c0d610
  Kazu Hirata authored Feb 14, 2021
  
  b4c0d610
- [llvm] Use llvm::is_contained (NFC) · 910e2d1e
  Kazu Hirata authored Feb 14, 2021
  
  910e2d1e
- [AVR] Fix a bug in 16-bit shifts · efb1cb75
  Ben Shi authored Feb 14, 2021
  efb1cb75
Feb 13, 2021
- [RISCV] Rename the RVVBaseAddr ComplexPattern to just BaseAddr and use it to... · 3520371d
  Craig Topper authored Feb 13, 2021
  3520371d
- [WebAssemblly] Fix rethrow's argument computation · 35f5f797
  Heejin Ahn authored Feb 11, 2021
  35f5f797
- [AMDGPU] Drop unnecessary const from a return type (NFC) · 96c90a6d
  Kazu Hirata authored Feb 12, 2021
  96c90a6d
- [FPEnv][ARM] Implement lowering of llvm.set.rounding · 816053bc
  Serge Pavlov authored Feb 11, 2021
  816053bc
- [RISCV] Move riscv_vfmv_v_f_vl patterns to RISCVInstrInfoVVLPatterns.td for... · 532d4bf0
  Craig Topper authored Feb 12, 2021
  532d4bf0