mov DWORD PTR [%ESP + 4], 1

instead of:

        mov %EAX, 1
        mov DWORD PTR [%ESP + 4], %EAX

llvm-svn: 13494

compiling things like 'add long %X, 1'.  The problem is that we were switching
the order of the operands for longs even though we can't fold them yet.

llvm-svn: 13451

llvm-svn: 13440

llvm-svn: 13439

syntactically loopify natural loops so that the GCC loop optimizer can find them.  This should *dramatically* improve the performance of CBE compiled code on targets that depend on GCC's loop optimizations (like PPC)

llvm-svn: 13438

llvm-svn: 13437

FindUsedTypes manipulation stuff out to be a seperate pass, and make the
main CWriter be a function pass now!

llvm-svn: 13435

llvm-svn: 13433

Print all PHI copies for successor blocks before the terminator, whether it be a conditional branch or switch.

llvm-svn: 13430

llvm-svn: 13425

Flesh out the SetCC support... which currently ends in a little bit
of unfinished code (which is probably completely hilarious) for
generating the condition value splitting the basic block up into 4
blocks, like this (clearly a better API is needed for this!):

       BB
   cond. branch
     /         /          R1=1    R2=0
     \      /
      \    /
    R=phi(R1,R2)

Other minor edits.

llvm-svn: 13423

llvm-svn: 13422

llvm-svn: 13421

llvm-svn: 13420

llvm-svn: 13419

Add support for branches (based loosely on X86/InstSelectSimple).
Add support for not visiting phi nodes in the first pass.
Add support for loading bools.
Flesh out support for stores.

llvm-svn: 13418

Disable the code that copies long constants to registers - it looks fishy.
Implement some simple casts: integral, smaller than longs, and equal-width
 or narrowing only.

llvm-svn: 13413

allows us to compile:

store float 10.0, float* %P

into:
        mov DWORD PTR [%EAX], 1092616192

instead of:

.CPItest_0:                                     # float 0x4024000000000000
.long   1092616192      # float 10
...
        fld DWORD PTR [.CPItest_0]
        fstp DWORD PTR [%EAX]

llvm-svn: 13409

against zero.  In particular, don't emit:

        mov %ESI, 0
        cmp %ECX, %ESI

instead, emit:

       test %ECX, %ECX

llvm-svn: 13407

llvm-svn: 13362

constant pool member's name.
This is intended to address Bug 333.

Also, fix an anachronistic usage of "M" as a parameter of type Function *.

llvm-svn: 13357

llvm-svn: 13355

div:
        mov %EDX, DWORD PTR [%ESP + 4]
        mov %ECX, 64
        mov %EAX, %EDX
        sar %EDX, 31
        idiv %ECX
        ret

to this:

div:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, %EAX
        sar %ECX, 5
        shr %ECX, 26
        mov %EDX, %EAX
        add %EDX, %ECX
        sar %EAX, 6
        ret

Note that the intel compiler is currently making this:

div:
        movl      4(%esp), %edx                                 #3.5
        movl      %edx, %eax                                    #4.14
        sarl      $5, %eax                                      #4.14
        shrl      $26, %eax                                     #4.14
        addl      %edx, %eax                                    #4.14
        sarl      $6, %eax                                      #4.14
        ret                                                     #4.14

Which has one less register->register copy.  (hint hint alkis :)

llvm-svn: 13354

llvm-svn: 13342

llvm-svn: 13304

Look at all of the pretty minuses. :)

llvm-svn: 13303

llvm-svn: 13297

llvm-svn: 13291

In InsertFPRegKills(), just check the MachineBasicBlock for successors
instead of its corresponding BasicBlock.

llvm-svn: 13213

LLVM CFG when trying to find the successors of BB.

llvm-svn: 13212

llvm-svn: 13211

llvm-svn: 13204

patch was graciously contributed by Vladimir Prus.

llvm-svn: 13185

renamed since they were last spiffed up, or they just never had proper comments
in the first place.

llvm-svn: 13148

llvm-svn: 13147

Include SparcV9RegisterInfo.h.
Add a getRegisterInfo() accessor and SparcV9RegisterInfo instance, just like
on the X86 target.

llvm-svn: 13146

functions for now). This automatically turns on the printing of machine
registers using their own real names, instead of goofy things like %mreg(42),
and allows us to migrate code incrementally to the new interface as we see fit.

The register file description it uses is hand-written, so that the register
numbers will match the ones that the SparcV9 target already uses.
Perhaps someday we'll tablegen it.

llvm-svn: 13145

llvm-svn: 13136

This prepares us to be able to de-virtualize and de-abstract it, and
take the register allocator bits out and move them into the register allocator
proper...

llvm-svn: 13127

llvm-svn: 13126