Commits · 2a6c871596ce8bdd23501a96fd22f0f16d3cfcad · Lorenzo Albano / LLVM bpEVL · GitLab

Jul 22, 2020
- [InstCombine] Move target-specific inst combining · 2a6c8715
  Sebastian Neubauer authored Jun 03, 2020
  2a6c8715
- [SLP]Add an extra test for vectorization of non-pow-2 trees, NFC. · be37f13e
  Alexey Bataev authored Jul 22, 2020
  
  be37f13e
- [NFC][Reduce] Add a test showing that we fail to to reduce single/last feature · 68922f7f
  Roman Lebedev authored Jul 22, 2020
  
  68922f7f
- [NFC][Reduce] Rewrite remove-funcs.ll to use FileCheck, make it less fragile · 4464d90e
  Roman Lebedev authored Jul 22, 2020
  
  4464d90e
- [ARM] Extra MVE select(binop) patterns · f8abecf3
  David Green authored Jul 22, 2020
  f8abecf3
- [ARM] Add patterns for select(p, BinOp(x, y), z) -> BinOpT(x, y,p z) · 3533e0a0
  David Green authored Jul 22, 2020
  3533e0a0
- [DebugInfo] Drop location ranges for variables which exist entirely outside the variable's scope · ce6de374
  OCHyams authored Jul 22, 2020
  ce6de374
- [llvm-readelf] - Introduce describe() helper functions. · 35202970
  Georgii Rymar authored Jul 21, 2020
  35202970
- [AMDGPU] Don't combine memory intrs to v3i16 · 2c659082
  Sebastian Neubauer authored Jul 21, 2020
  2c659082
- [llvm-readelf/readobj] - Fix the behavior when a sections is included in two... · 066e209c
  Georgii Rymar authored Jul 20, 2020
  066e209c
- [PowerPC] fixupIsDeadOrKill start and end in different block fixing · 36f9fe2d
  Chen Zheng authored Jul 22, 2020
  36f9fe2d
- [llvm-readobj/readelf] - Don't fail dumping when unable to read the name of the SHT_DYNSYM section. · 54ef74f7
  Georgii Rymar authored Jul 20, 2020
  54ef74f7
- [Test] Add more simple tests for PR46786 · c1d8e392
  Max Kazantsev authored Jul 22, 2020
  
  c1d8e392
- [AArch64][SVE] Correctly allocate scavenging slot in presence of SVE. · bef56f7f
  Sander de Smalen authored Jul 22, 2020
  bef56f7f
- [ARM] Predicated binary operation tests. NFC · a4bbc3b7
  David Green authored Jul 22, 2020
  
  a4bbc3b7
- [PowerPC] Extend .reloc directive on PowerPC · e0a372ff
  Stefan Pintilie authored Jul 21, 2020
  e0a372ff
- [Thumb] set code alignment for 16-bit load from constant pool · 94e4e37d
  Simon Wallis authored Jul 22, 2020
  94e4e37d
- [SCEV] Remove premature assert. PR46786 · b96114c1
  Max Kazantsev authored Jul 22, 2020
  b96114c1
- AMDGPU: Simplify f16 to i64 custom lowering · 44967fc6
  Petar Avramovic authored Jul 22, 2020
  44967fc6
- [ARM] Fix Asm/Disasm of TBB/TBH instructions · 3a341946
  David Spickett authored Jul 16, 2020
  3a341946
- [SimplifyCFG] Do not create unneeded PR Phi in block with convergent calls · 360ab707
  Max Kazantsev authored Jul 22, 2020
  360ab707
- [PowerPC] Fix wrong codegen when stack pointer has to realign performing dynalloc · c3f9697f
  Kai Luo authored Jul 22, 2020
  c3f9697f
- [PowerPC] Fix wrong codegen when stack pointer has to realign in prologue · 89122522
  Kai Luo authored Jul 22, 2020
  89122522
- [PowerPC] Fix the implicit operands in PredicateInstruction() · 9bbf0ecf
  Kang Zhang authored Jul 22, 2020
  9bbf0ecf
- [DWARFYAML] Use yaml::Hex64 rather than uint64_t as length. NFC. · e4ef948a
  Xing GUO authored Jul 22, 2020
  e4ef948a
- [PowerPC] add store (load float*) pattern to isProfitableToHoist · e8425b27
  Chen Zheng authored Jul 21, 2020
  e8425b27
- [ValueTracking] Fix incorrect handling of canCreateUndefOrPoison · ace0bf74
  Juneyoung Lee authored Jul 22, 2020
  ace0bf74
- [PDB][NativeSession] Clean up some things in NativeSession. · 0881d0be
  Amy Huang authored Jul 21, 2020
  0881d0be
- [PowerPC][Power10] Add Vector Multiply/Mod/Divide Instruction Definitions and MC Tests · 1eb279d2
  Amy Kwan authored Jul 21, 2020
  1eb279d2
- Revert "[AArch64][GlobalISel] Add post-legalize combine for sext_inreg(trunc(sextload)) -> copy" · 79154442
  Amara Emerson authored Jul 21, 2020
  79154442
- [AArch64][GlobalISel] Fix TLS accesses clobbering registers incorrectly. · f1ae96d9
  Amara Emerson authored Jul 14, 2020
  f1ae96d9
- AMDGPU/GlobalISel: Add some baseline degenerate call argument tests · 7a669130
  Matt Arsenault authored Jul 21, 2020
  
  7a669130
- AMDGPU/GlobalISel: Fix not erasing inst when lowering G_FRINT · b2589200
  Matt Arsenault authored Jul 21, 2020
  
  b2589200
- GlobalISel: Legalize G_FPOWI · 7cd8a025
  Matt Arsenault authored Jul 17, 2020
  
  7cd8a025
- GlobalISel: Translate llvm.powi intrinsic · 7941dc50
  Matt Arsenault authored Jul 17, 2020
  7941dc50
- AMDGPU: Start interpreting byref on kernel arguments · 1168119c
  Matt Arsenault authored May 07, 2020
  1168119c
Jul 21, 2020
- [SCCP] Add switch+range tests (NFC) · ef868a84
  Nikita Popov authored Jul 21, 2020
  
  ef868a84
- [X86][AVX] getTargetShuffleMask - don't decode VBROADCAST(EXTRACT_SUBVECTOR(X,0)) patterns. · 5b5dc244
  Simon Pilgrim authored Jul 21, 2020
  5b5dc244
- [llvm-libtool-darwin] Allow flattening archives · 9e783716
  Sameer Arora authored Jul 02, 2020
  9e783716
- DebugInfo: Add missing comment from llvm/test/DebugInfo/X86/debug-macro-dwo.ll · 2892bec5
  David Blaikie authored Jul 21, 2020
  2892bec5