Commits · 2c47b8847ec75c25187e9819abd85cc9e908d742 · Lorenzo Albano / LLVM bpEVL · GitLab

Jul 13, 2021
- Revert "[llvm] Add enum iteration to Sequence" · 2c47b884
  Guillaume Chatelet authored Jul 13, 2021
  2c47b884
- [OpaquePtr] Use byval type more · ab5693aa
  Arthur Eubanks authored Jul 13, 2021
  
  ab5693aa
- [OpaquePtr] Get load/store type without PointerType::getElementType() · 113a8079
  Arthur Eubanks authored Jul 13, 2021
  
  113a8079
- [OpaquePtr] Use GlobalValue::getValueType() more · 693bc04b
  Arthur Eubanks authored Jul 13, 2021
  
  693bc04b
- [OpaquePtr] Use AllocaInst::getAllocatedType() · b25aca50
  Arthur Eubanks authored Jul 13, 2021
  
  b25aca50
- [RISCV] Support machine constraint "S" · 3d89fb4d
  Fangrui Song authored Jul 13, 2021
  3d89fb4d
- [llvm] Add enum iteration to Sequence · a006af5d
  Guillaume Chatelet authored Jul 13, 2021
  a006af5d
- [PowerPC] Fix L[D|W]ARX Implementation · f1aca5ac
  Albion Fung authored Jul 13, 2021
  f1aca5ac
- [PowerPC][NFC] Power ISA features for Semachecking · 10e0cdfc
  Victor Huang authored Jul 13, 2021
  10e0cdfc
- AMDGPU: Promote signext/zeroext i16 shader returns · fb44c322
  Matt Arsenault authored Jul 12, 2021
  fb44c322
- GlobalISel: Use extension instead of merge with undef in common case · 222fde1e
  Matt Arsenault authored Jul 11, 2021
  222fde1e
- GlobalISel: Remove getIntrinsicID utility function · 77a608d9
  Matt Arsenault authored Jul 11, 2021
  77a608d9
- Mips/GlobalISel: Use more standard call lowering infrastructure · 121541fd
  Matt Arsenault authored Jul 06, 2021
  121541fd
- Mips: Mark special case calling convention handling as custom · 6a3904f1
  Matt Arsenault authored Jul 08, 2021
  6a3904f1
- [InstCombine] Fold lshr/ashr(or(neg(x),x),bw-1) --> zext/sext(icmp_ne(x,0)) (PR50816) · b2f6cf14
  Simon Pilgrim authored Jul 13, 2021
  b2f6cf14
- [X86][SSE] X86ISD::FSETCC nodes (cmpss/cmpsd) return a 0/-1 allbits signbits result (REAPPLIED) · 3cee36c5
  Simon Pilgrim authored Jul 13, 2021
  3cee36c5
- [AMDGPU] Handle s_branch to another section. · b205f2bb
  Hafiz Abid Qadeer authored Jul 13, 2021
  b205f2bb
- [AMDGPU] Optimize VGPR LiveRange in waterfall loops · ad2c66ec
  Sebastian Neubauer authored Jul 06, 2021
  ad2c66ec
- [AMDGPU] Mark waterfall loops as SI_WATERFALL_LOOP · 9d72c0ad
  Sebastian Neubauer authored Jul 06, 2021
  9d72c0ad
- AArch64: use 4-byte slots for arm64_32 pointers in a tail call · 7802f62b
  Tim Northover authored Jun 28, 2021
  
  7802f62b
- [RISCV] Pass undef VECTOR_SHUFFLE indices on to BUILD_VECTOR · d991b721
  Fraser Cormack authored Jun 23, 2021
  d991b721
- [remangleIntrinsicFunction] Detect and resolve name clash · 90a6bb30
  Jeroen Dobbelaere authored Jul 13, 2021
  90a6bb30
- [NFC] Do not track calls to inlined intrinsics in IFI. · 1d803005
  Jeroen Dobbelaere authored Jul 13, 2021
  1d803005
- [SelectionDAG] Check use before combining into USUBSAT · 954a15d6
  Qiu Chaofan authored Jul 13, 2021
  954a15d6
- [AMDGPU] Make some VOP1 instructions rematerializable · d46d534d
  Stanislav Mekhanoshin authored Jul 09, 2021
  d46d534d
- [PowerPC] Fix typo in vector shuffle combining · 6fd9c190
  Qiu Chaofan authored Jul 13, 2021
  6fd9c190
- [SimplifyCFG] Fix SimplifyBranchOnICmpChain to be undef/poison safe. · e338d08a
  hyeongyu kim authored Jul 13, 2021
  e338d08a
- [ARM] Introduce MVEEXT ISel lowering · ca781510
  David Green authored Jul 13, 2021
  ca781510
- [NFC] Edit the comment in M68kInstrInfo::ExpandMOVSZX_RM · d7d9c577
  hyeongyu kim authored Jul 13, 2021
  
  d7d9c577
- Revert "[X86][SSE] X86ISD::FSETCC nodes (cmpss/cmpsd) return a 0/-1 allbits signbits result" · 606551ee
  Vitaly Buka authored Jul 12, 2021
  606551ee
- [GlobalISel] Handle more types in narrowScalar for eq/ne G_ICMP · 47d0780f
  Jessica Paquette authored Jun 29, 2021
  47d0780f
- [OpaquePtr][ISel] Use ArgListEntry::IndirectType more · 7987c462
  Arthur Eubanks authored Jul 12, 2021
  
  7987c462
- [OpaquePointers][ThreadSanitizer] Cleanup calls to PointerType::getElementType() · 0e6424ac
  Arthur Eubanks authored Jul 09, 2021
  0e6424ac
- DebugInfo: Use debug_rnglists.dwo for ranges in debug_info.dwo when parsing DWARFv5 · ea91749f
  David Blaikie authored Jul 12, 2021
  ea91749f
- [AArch64] Dump a little more info about unimplemented reg-to-reg copies. NFC · 6611fbc6
  Jon Roelofs authored Jul 12, 2021
  
  6611fbc6
- [AArch64] Optimize overflow checks for [s|u]mul.with.overflow.i32. · 6c04b7dd
  Eli Friedman authored Jul 12, 2021
  6c04b7dd
Jul 12, 2021
- [SelectionDAG][RISCV] Support @llvm.vscale.i64() on 32-bit targets. · ec1cdee6
  Eli Friedman authored Jul 12, 2021
  ec1cdee6
- [PowerPC] Fix the splat immediate in PPCMIPeephole depending on if we have an... · 35909ff6
  Amy Kwan authored Jul 12, 2021
  35909ff6
- [Attributes] Determine attribute properties from TableGen data · 7ed3e878
  Nikita Popov authored Jul 11, 2021
  7ed3e878
- [WebAssembly] fix typo in range check for Asm locals · 1689d14e
  Wouter van Oortmerssen authored Jul 12, 2021
  
  1689d14e