of BUILD_VECTORS that only have two unique elements:

1. The previous code was nondeterminstic, because it walked a map in
   SDOperand order, which isn't determinstic.
2. The previous code didn't handle the case when one element was undef
   very well.  Now we ensure that the generated shuffle mask has the
   undef vector on the RHS (instead of potentially being on the LHS)
   and that any elements that refer to it are themselves undef.  This
   allows us to compile CodeGen/X86/vec_set-9.ll into:

_test3:
	movd	%rdi, %xmm0
	punpcklqdq	%xmm0, %xmm0
	ret

instead of:

_test3:
	movd	%rdi, %xmm1
	#IMPLICIT_DEF %xmm0
	punpcklqdq	%xmm1, %xmm0
	ret

... saving a register.

llvm-svn: 48060

_test3:
	movd	%rdi, %xmm1
	#IMPLICIT_DEF %xmm0
	punpcklqdq	%xmm1, %xmm0
	ret

instead of:

_test3:
	#IMPLICIT_DEF %rax
	movd	%rax, %xmm0
	movd	%rdi, %xmm1
	punpcklqdq	%xmm1, %xmm0
	ret

This is still not ideal.  There is no reason to two xmm regs.

llvm-svn: 48058

2) Don't try to insert an i64 value into the low part of a 
   vector with movq on an x86-32 target.  This allows us to 
   compile:

__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:

_doload64:
	movaps	LCPI1_0, %xmm0
	ret

instead of:

_doload64:
	subl	$28, %esp
	movl	$0, 4(%esp)
	movl	$1, (%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret

llvm-svn: 48057

SCALAR_TO_VECTOR on paths that end up not using it.

llvm-svn: 48056

llvm-svn: 48055

llvm-svn: 48054

llvm-svn: 48053

llvm-svn: 48052

which is simpler to use and provide.

llvm-svn: 48051

different widths.  Start simplifying TargetInfo accessor methods.

llvm-svn: 48050

llvm-svn: 48049

llvm-svn: 48048

llvm-svn: 48047

it tries to initialize them.

llvm-svn: 48046

llvm-svn: 48045

llvm-svn: 48044

are looking pretty good now.

llvm-svn: 48043

Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.

llvm-svn: 48042

llvm-svn: 48041

kills the sub-register.

llvm-svn: 48038

llvm-svn: 48037

that are not related to error nodes.

Fixed bug where we did not detect some NULL dereferences.

Added "ExplodedGraph::Trim" to trim all nodes that cannot transitively reach
a set of provided nodes.

Fixed subtle bug in ExplodedNodeImpl where we could create predecessor
iterators that included the mangled "sink" bit.  The better fix is to integrate
this bit into the void* for the wrapped State, not the NodeGroups representing
a node's predecessors and successors.

llvm-svn: 48036

llvm-svn: 48035

llvm-svn: 48034

llvm-svn: 48033

llvm-svn: 48032

information.

llvm-svn: 48031

by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.

llvm-svn: 48030

llvm-svn: 48029

but there are bugs.

llvm-svn: 48028

llvm-svn: 48027

with 32 or 64-bit operands/results.

llvm-svn: 48026

llvm-svn: 48025

Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI.

llvm-svn: 48024

llvm-svn: 48023

llvm-svn: 48022

llvm-svn: 48021

llvm-svn: 48020

llvm-svn: 48019

llvm-svn: 48018