OpenMP 4.0 "target" directives. This will need more work for
generality, but we want to get it out and visible to the community.

llvm-svn: 205909

This commit adds intrinsics and codegen support for the surface read/write and texture read instructions that take an explicit sampler parameter. Codegen operates on image handles at the PTX level, but falls back to direct replacement of handles with kernel arguments if image handles are not enabled. Note that image handles are explicitly disabled for all target architectures in this change (to be enabled later).

llvm-svn: 205907

[NVPTX] Add support for addrspacecast in global variable initializers, including emitting generic() when casting to address space 0.

llvm-svn: 205906

This also fixes a bug in the annotation cache where the cache will not be cleared between modules if multiple modules are compiled in the same process.

llvm-svn: 205905

Calling mutex_lock from one thread and then mutex_unlock from another is
not permitted.  Replace the awkward mutex usage with a mutex and
condition variable.

llvm.org/pr18061                                                            

llvm-svn: 205900

llvm-svn: 205899

llvm-svn: 205898

llvm-svn: 205897

llvm-svn: 205896

llvm-svn: 205895

llvm-svn: 205894

llvm-svn: 205893

llvm-svn: 205892

llvm-svn: 205891

llvm-svn: 205890

llvm-svn: 205889

llvm-svn: 205888

llvm-svn: 205887

[ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions.

llvm-svn: 205886

llvm-svn: 205885

llvm-svn: 205884

[ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value.

llvm-svn: 205883

llvm-svn: 205882

[ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear.

llvm-svn: 205881

llvm-svn: 205880

llvm-svn: 205879

llvm-svn: 205878

llvm-svn: 205877

llvm-svn: 205876

llvm-svn: 205875

[ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value.

llvm-svn: 205874

llvm-svn: 205873

llvm-svn: 205872

llvm-svn: 205871

llvm-svn: 205870

[ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS.

llvm-svn: 205869

[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.

llvm-svn: 205868

[ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent.

llvm-svn: 205867

[ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over.

llvm-svn: 205866

[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.

llvm-svn: 205865