Commits · 3b77e2737c8545aa628e1d2cff5799db033f7081 · Lorenzo Albano / LLVM bpEVL · GitLab

Jul 26, 2021
- [SVE] Use reg+reg addressing mode for immediate offsets. · 3b77e273
  Paul Walker authored Jul 22, 2021
  3b77e273
- [AArch64][SVE] Break false dependencies for inactive lanes of unary operations · 81eafb8a
  Bradley Smith authored Jul 08, 2021
  81eafb8a
- [SystemZ] Add support for new cpu architecture - arch14 · 8cd8120a
  Ulrich Weigand authored Jul 20, 2021
  8cd8120a
- [AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset · 59f68652
  Jay Foad authored Jul 21, 2021
  59f68652
- [AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset · 9ac10658
  Jay Foad authored Jul 19, 2021
  9ac10658
- [ARM] Ensure correct regclass in distributing postinc · 010f8e30
  David Green authored Jul 26, 2021
  010f8e30
- AArch64: support i128 (& larger) returns in GlobalISel · a487a49a
  Tim Northover authored Jul 26, 2021
  
  a487a49a
- [AArch65][SVE] Remove vector_splice from AddedComplexity pattern · bf28111e
  Caroline Concatto authored Jul 26, 2021
  bf28111e
- [SVE][AArch64] Improve code generation for vector_splice for Imm > 0 · 0bfc26e3
  Caroline Concatto authored Jul 19, 2021
  0bfc26e3
- [AArch64][SVE] Improve code generation for vector_splice for Imm == -1 · 73e4e9cd
  Caroline Concatto authored Jul 06, 2021
  73e4e9cd
- [X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets · c8472db0
  Simon Pilgrim authored Jul 26, 2021
  c8472db0
- [AArch64][AsmParser] NFC: Parser.getTok().getLoc() -> getLoc() · e6ff9179
  Cullen Rhodes authored Jul 26, 2021
  e6ff9179
- [Analysis] Add simple cost model for strict (in-order) reductions · 0aff1798
  David Sherwood authored Jul 07, 2021
  0aff1798
Jul 25, 2021
- [X86][AVX] Add getBROADCAST_LOAD helper function. NFCI. · 1cfecf4f
  Simon Pilgrim authored Jul 25, 2021
  1cfecf4f
- [AArch64] Fix Local Deallocation for Homogeneous Prolog/Epilog · 6530ea40
  Kyungwoo Lee authored Jul 25, 2021
  6530ea40
- [X86][SSE] LowerRotate - perform modulo on the amount splat source directly. · b95f66ad
  Simon Pilgrim authored Jul 25, 2021
  b95f66ad
- [x86] improve CMOV codegen by pushing add into operands, part 2 · 1ce05ad6
  Sanjay Patel authored Jul 25, 2021
  1ce05ad6
- [X86][AVX] Adjust AllowBWIVPERMV3 tolerance to account for VariableCrossLaneShuffleDepth · 15b883f4
  Simon Pilgrim authored Jul 25, 2021
  15b883f4
- [AArch64][GlobalISel] Widen non-pow-2 types for shifts before clamping. · acbc0c5f
  Amara Emerson authored Jul 24, 2021
  acbc0c5f
Jul 24, 2021
- [RISCV] Custom lower (i32 (fptoui/fptosi X)). · c63dbd85
  Craig Topper authored Jul 24, 2021
  c63dbd85
- [AVR] Only support sp, r0 and r1 in llvm.read_register · 4d7f5c0a
  Ayke van Laethem authored Feb 18, 2021
  4d7f5c0a
- [AVR] Fix rotate instructions · 41f905b2
  Ayke van Laethem authored Feb 18, 2021
  41f905b2
- [AVR] Expand large shifts early in IR · 6aa9e746
  Ayke van Laethem authored Feb 14, 2021
  6aa9e746
- [AVR] Improve 8/16 bit atomic operations · 431a9414
  Ayke van Laethem authored Feb 20, 2021
  431a9414
- [AVR] Set R31R30 as clobbered after ADJCALLSTACKDOWN · 8544ce80
  Ayke van Laethem authored Mar 02, 2021
  8544ce80
- [AVR] Do not chain stores in call frame setup · feda08b7
  Ayke van Laethem authored Mar 03, 2021
  feda08b7
- [llvm] Inline getAssociatedFunction() in LLVM_DEBUG. · edb05d55
  Alexander Belyaev authored Jul 24, 2021
  edb05d55
- [GlobalISel] Add GUnmerge, GMerge, GConcatVectors, GBuildVector abstractions. NFC. · 5ec0f051
  Amara Emerson authored Jul 23, 2021
  5ec0f051
- [AMDGPU] Deduce attributes with the Attributor · 96709823
  Kuter Dinel authored Jun 27, 2021
  96709823
Jul 23, 2021
- [WebAssembly] Codegen for pmin and pmax · 85157c00
  Thomas Lively authored Jul 23, 2021
  85157c00
- [WebAssembly][NFC] Simplify SIMD bitconvert pattern · 39c0e4af
  Thomas Lively authored Jul 23, 2021
  39c0e4af
- [RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the... · 5edccc45
  Craig Topper authored Jul 23, 2021
  5edccc45
- [X86] Fix a bug in TEST with immediate creation · cc6d302c
  Craig Topper authored Jul 22, 2021
  cc6d302c
- [llvm][sve] Silence unused variable warning in Release builds. NFC · dd70cd08
  Benjamin Kramer authored Jul 23, 2021
  
  dd70cd08
- [x86] improve CMOV codegen by pushing add into operands · f060aa1c
  Sanjay Patel authored Jul 23, 2021
  f060aa1c
- [llvm][sve] Lowering for VLS truncating stores · 1528a4d4
  David Truby authored Jul 12, 2021
  1528a4d4
- [X86][AVX] lowerV2X128Shuffle - attempt to recognise broadcastf128 subvector load · 71d0fd35
  Simon Pilgrim authored Jul 23, 2021
  71d0fd35
- [AArch64] Add worst case shuffle costs · 38986c67
  David Green authored Jul 23, 2021
  38986c67
- [AMDGPU] Fix running ResourceUsageAnalysis · 2f153199
  Sebastian Neubauer authored Jul 21, 2021
  2f153199
- [AMDGPU] Add maximum NSA size limit ISA feature · 7d4baf25
  Carl Ritson authored Jul 22, 2021
  7d4baf25