Commits · 529f42331e425aa812a48ab385dd00a67be9ea37 · Lorenzo Albano / LLVM bpEVL · GitLab

Mar 19, 2018
- [SCEV] Re-land: Fix isKnownPredicate · 529f4233
  Serguei Katkov authored Mar 19, 2018
  529f4233
- [X86] Merge XADD8rr regular expression with XADD16rr/XADD32rr/XADD64rr in a... · e18fbab9
  Craig Topper authored Mar 19, 2018
  e18fbab9
- [X86] Add ADD16i16/ADD32i32/ADD64i32 and similar to the scheduler models to match ADD8i8. · d10ceffa
  Craig Topper authored Mar 19, 2018
  d10ceffa
- [X6] Remove two unused InstrItinClass · e9c99d32
  Craig Topper authored Mar 19, 2018
  e9c99d32
- remainder: Port from amd builtins · 5b10494f
  Jan Vesely authored Mar 19, 2018
  5b10494f
- [X86] Use IIC_CMOV64_RR/RM on 64-bit cmov instructions. · 793733a6
  Craig Topper authored Mar 19, 2018
  793733a6
- [X86] Merge 32 and 64-bit RORX/SHLX/SARX/SHRX into single regular expressions in scheduler models. · 9b60dcb2
  Craig Topper authored Mar 19, 2018
  9b60dcb2
- [X86] Merge 8-bit instructions into instregex with 16/32/64 instructions in... · 13a1650d
  Craig Topper authored Mar 19, 2018
  13a1650d
- [AVR] Lower i128 divisions to runtime library calls · a35ee706
  Dylan McKay authored Mar 19, 2018
  a35ee706
Mar 18, 2018
- [Mips] Remove duplicate lines from MipsScheduleP5600.td and enable FullInstRWOverlapCheck. · f545cfee
  Craig Topper authored Mar 18, 2018
  f545cfee
- [AArch64] Fix a few InstRWs in the A53 scheduler model and enable FullInstRWOverlapCheck. · 75aeb62e
  Craig Topper authored Mar 18, 2018
  75aeb62e
- [SelectionDAG] Don't default the SelectionDAG* parameter to SDValue::dump to... · f7fdfb3f
  Craig Topper authored Mar 18, 2018
  f7fdfb3f
- Move the codebase to use: DWARFCompileUnit -> DWARFUnit · c4d65751
  Jan Kratochvil authored Mar 18, 2018
  c4d65751
- DWARFUnit split out of DWARFCompileUnit · 2ccddfe3
  Jan Kratochvil authored Mar 18, 2018
  2ccddfe3
- [TableGen] When trying to reuse a scheduler class for instructions from an... · e1d6a4df
  Craig Topper authored Mar 18, 2018
  e1d6a4df
- [X86][Btver2] Fix crc32 schedule costs · 203876f1
  Simon Pilgrim authored Mar 18, 2018
  203876f1
- Updated C++2a status with changes from Jacksonville WG21 meeting · c8faf3a9
  Marshall Clow authored Mar 18, 2018
  c8faf3a9
- [X86][Btver2] Add crc32 resource tests · 13cd3b09
  Simon Pilgrim authored Mar 18, 2018
  13cd3b09
- [X86][Btver2] FADD/FHADD ymm instructions are double pumped on the JFPA functional pipe · c3db8c7c
  Simon Pilgrim authored Mar 18, 2018
  c3db8c7c
- [X86][Btver2] Float bitwise ymm instructions are double pumped on the JFPX... · 036cc826
  Simon Pilgrim authored Mar 18, 2018
  036cc826
- Resolve unused variable 'VR' warning in RetainCountChecker.cpp · fe357865
  Bjorn Pettersson authored Mar 18, 2018
  fe357865
- [X86][Btver2] F16C instructions are performed on the JSTC functional pipe · 87d2f746
  Simon Pilgrim authored Mar 18, 2018
  87d2f746
- [LICM] Salvage DI from dying Instructions · 3a589103
  Anastasis Grammenos authored Mar 18, 2018
  3a589103
- [InstCombine] peek through unsigned FP casts for zero-equality compares (PR36682) · e6da3063
  Roman Lebedev authored Mar 18, 2018
  e6da3063
- [llvm-mca] Allow the definition of multiple register files. · e64f3b10
  Andrea Di Biagio authored Mar 18, 2018
  e64f3b10
- [InstCombine] add nnan requirement for sqrt(x) * sqrt(y) -> sqrt(x*y) · 63b10289
  Sanjay Patel authored Mar 18, 2018
  63b10289
- [InstSimplify] loosen FMF for sqrt(X) * sqrt(X) --> X · 95ec4a4d
  Sanjay Patel authored Mar 18, 2018
  95ec4a4d
- [X86][Btver2] Strip default latency/resource values. NFCI. · 54199220
  Simon Pilgrim authored Mar 18, 2018
  54199220
- [X86][Btver2] SSE4A EXTRQ/INSERTQ instructions are performed on the JVALU0/JVALU1 functional pipes · 40f6d6ad
  Simon Pilgrim authored Mar 18, 2018
  40f6d6ad
- [X86][Btver2] Modelled float bitwise instructions as being performed on the... · e16790b1
  Simon Pilgrim authored Mar 18, 2018
  e16790b1
- [dsymutil] Fix add_llvm_tool_symlink · 163326d1
  Jonas Devlieghere authored Mar 18, 2018
  163326d1
- [X86][Btver2] Correctly distinguish between scheduling pipe and functional... · e409f84e
  Simon Pilgrim authored Mar 18, 2018
  e409f84e
- [dsymutil] Rename llvm-dsymutil -> dsymutil · a6ef1abc
  Jonas Devlieghere authored Mar 18, 2018
  a6ef1abc
- [X86][Btver2] Merge equivalent VBLENDVY + VPERMILY schedule groups · f86d48b3
  Simon Pilgrim authored Mar 18, 2018
  f86d48b3
- [X86][Btver2] Add llvm-mca tests to show pipe resource usage of most vector instructions · 0ba4a0f3
  Simon Pilgrim authored Mar 18, 2018
  0ba4a0f3
- [X86] Fix a bunch of overlapping regular expressions in the scheduler models. · 2d451e73
  Craig Topper authored Mar 18, 2018
  2d451e73
- [X86] Fix a couple typos in the Zen scheduler model. · 86b02cf0
  Craig Topper authored Mar 18, 2018
  86b02cf0
- [TableGen] Remove unnecessary uses of make_range. · 93dd77d2
  Craig Topper authored Mar 18, 2018
  93dd77d2
- [TableGen] Move some variables into for loop declaration. NFC · 7f31e735
  Craig Topper authored Mar 18, 2018
  7f31e735
- [X86] Remove MMX_MASKMOVQ64 and VMASKMOVDQU from scheduler models. · 89dcda3e
  Craig Topper authored Mar 18, 2018
  89dcda3e