Commits · 5b3a5cf6b07e3e624dfc96bf3800c300abe950ed · Lorenzo Albano / LLVM bpEVL · GitLab

Jul 20, 2016
- [NVPTX] Renamed NVPTXLowerKernelArgs -> NVPTXLowerArgs. NFC. · 7e9c9a65
  Artem Belevich authored Jul 20, 2016
  7e9c9a65
- [AArch64][FastISel] Select -O0 legal cmpxchg. · a0cdd790
  Ahmed Bougacha authored Jul 20, 2016
  a0cdd790
- [AArch64][FastISel] Select atomic stores into STLR. · b0674d11
  Ahmed Bougacha authored Jul 20, 2016
  b0674d11
- GlobalISel: implement low-level type with just size & vector lanes. · 62ae568b
  Tim Northover authored Jul 20, 2016
  62ae568b
- [NVPTX] deal with all aggregate return types. · 74158b50
  Artem Belevich authored Jul 20, 2016
  74158b50
- [NVPTX] Improve lowering of byval args of device functions. · b2e76a5e
  Artem Belevich authored Jul 20, 2016
  b2e76a5e
- AMDGPU: Fix bug causing crash due to invalid opencl version metadata. · 4b1d9f7f
  Yaxun Liu authored Jul 20, 2016
  4b1d9f7f
- [X86][SSE] Add cost model values for CTPOP of vectors · 1b4f511a
  Simon Pilgrim authored Jul 20, 2016
  1b4f511a
- [ARM] Skip inline asm memory operands in DAGToDAGISel · f345d40a
  Diana Picus authored Jul 20, 2016
  f345d40a
- [AVX512] Add a missing NoVLX to give priority to the AVX512 version of the pattern. · 09b99c3a
  Craig Topper authored Jul 20, 2016
  09b99c3a
- [X86] Use 'HasAVX1Only' to properly give priority to the AVX2 version without... · 7a95428f
  Craig Topper authored Jul 20, 2016
  7a95428f
- [X86] Create some multiclasses to reduce the repeated patterns for... · cde436a6
  Craig Topper authored Jul 20, 2016
  cde436a6
- [X86] Create some wrapper multiclasses to create AVX and SSE shift... · 55913ead
  Craig Topper authored Jul 20, 2016
  55913ead
- Revert "Disable this-return argument forwarding on ARM/AArch64" · 5d261277
  David Majnemer authored Jul 20, 2016
  5d261277
- AMDGPU: Change fdiv lowering based on !fpmath metadata · a1fe17c9
  Matt Arsenault authored Jul 19, 2016
  a1fe17c9
- [AArch64] Properly validate the reciprocal estimation. · 238fa765
  Evandro Menezes authored Jul 19, 2016
  238fa765
Jul 19, 2016
- [AMDGPU] Remove spurious line (should've been removed in r276029). · 63e59680
  Davide Italiano authored Jul 19, 2016
  63e59680
- [AMDGPU] Remove dead code. · 1576e385
  Davide Italiano authored Jul 19, 2016
  1576e385
- ARM: move feature for Thumb2 pkhbt/pkhtb onto architectures. · 554fbd05
  Tim Northover authored Jul 19, 2016
  554fbd05
- AMDGPU: Only use legal inline immediates with kill pseudo · 03006fd3
  Matt Arsenault authored Jul 19, 2016
  03006fd3
- [X86][SSE] Reimplement SSE fp2si conversion intrinsics instead of using generic IR · 0ea8d275
  Simon Pilgrim authored Jul 19, 2016
  0ea8d275
- [ARM] Refactor Thumb2 Mul and Mla instr descs · 6ca4bbb0
  Sam Parker authored Jul 19, 2016
  6ca4bbb0
- [AArch64] PredictableSelectIsExpensive for Vulcan. · 1bfca191
  Pankaj Gode authored Jul 19, 2016
  1bfca191
- Add support for tlsldm assembler operator to ARM target · cbcecca5
  Peter Smith authored Jul 19, 2016
  cbcecca5
- [mips][ias] R_MIPS_GOT_(PAGE|OFST) do not need symbols · 38784128
  Daniel Sanders authored Jul 19, 2016
  38784128
- [mips] Correct label prefixes for N32 and N64. · 6a73883c
  Daniel Sanders authored Jul 19, 2016
  6a73883c
- AVX-512: Fixed BT instruction selection. · 2c0780b8
  Elena Demikhovsky authored Jul 19, 2016
  2c0780b8
- [AVX512] Give priority to EVEX encoded PSHUFB over the VEX versions. · d6ca1dc4
  Craig Topper authored Jul 19, 2016
  d6ca1dc4
- [X86] Remove superfluous parameter from a multiclass. All instantiations passed the same value. · 592dc307
  Craig Topper authored Jul 19, 2016
  592dc307
- [X86] Rename VINSERTzrr to use a capital Z to match other instructions. NFC · 6189d3ec
  Craig Topper authored Jul 19, 2016
  6189d3ec
- AMDGPU/SI: Fix SI scheduler refcount issue · fe358066
  Matt Arsenault authored Jul 19, 2016
  fe358066
- AMDGPU: Expand register indexing pseudos in custom inserter · cb540bc0
  Matt Arsenault authored Jul 19, 2016
  cb540bc0
Jul 18, 2016
- [NVPTX] Make sure we adjust alignment at all call sites · 9f97dcb0
  Artem Belevich authored Jul 18, 2016
  9f97dcb0
- [NVPTX] Force minimum alignment of 4 for byval arguments of device-side functions. · 052b1ed2
  Artem Belevich authored Jul 18, 2016
  052b1ed2
- Revert "[ARM] Skip inline asm memory operands in DAGToDAGISel" · c93e10fc
  Vitaly Buka authored Jul 18, 2016
  c93e10fc
- AMDGPU: Remove pointless dyn_cast_or_null · 210b7cf3
  Matt Arsenault authored Jul 18, 2016
  210b7cf3
- AMDGPU: Fix missing switch case warning · b51dcb97
  Matt Arsenault authored Jul 18, 2016
  b51dcb97
- AMDGPU: Add intrinsic for s_flbit_i32/v_ffbh_i32 · c96e1def
  Matt Arsenault authored Jul 18, 2016
  c96e1def
- AMDGPU/R600: Replace barrier intrinsics · 4c519d35
  Matt Arsenault authored Jul 18, 2016
  4c519d35
- AMDGPU: Remove dead check in AMDGPUPromoteAlloca · efb24540
  Matt Arsenault authored Jul 18, 2016
  efb24540