calls if we haven't been able to lower them any
other way.

Fixes rdar://9090077 and rdar://9210061

llvm-svn: 133288

llvm-svn: 133275

and other backward compatibility hacks.

llvm-svn: 133273

to functions and call/invokes, not to types.

llvm-svn: 133266

llvm-svn: 133260

llvm-svn: 133256

* rounding modes for fp add, mul, sub now use .rn
* float -> int rounding correctly uses .rzi not .rni
* 32bit fdiv for sm13 uses div.rn (instead of div.approx)
* 32bit fdiv for sm10 now uses div (instead of div.approx)

Approx is not IEEE 754 compatible (and should be optionally set by a flag to the backend instead). The .rn rounding modifier is the PTX default anyway, but it's better to be explicit.

All these modifiers should be available by using __fmul_rz functions for example, but support will need to be added for this in the backend.

Patch by Dan Bailey

llvm-svn: 133253

needed since llvm-gcc 3.4 days.

llvm-svn: 133248

remove asmparser support for the old getresult instruction, which has been subsumed by extractvalue.

llvm-svn: 133247

was replaced with return of a "first class aggregate".

llvm-svn: 133245

llvm-svn: 133244

syntax and has been long obsolete.  As usual, updating the tests is the nasty
part of this.

llvm-svn: 133242

are either unreduced or only test old syntax.

llvm-svn: 133228

tail call pseudoinstruction. This fixes <rdar://problem/9624333>.

llvm-svn: 133227

In Thumb mode we cannot handle GPR virtual registers, even though some
instructions can. When isel is lowering a CopyFromReg, it should limit
itself to subclasses of getRegClassFor(VT).

<rdar://problem/9624323>

llvm-svn: 133210

llvm-svn: 133205

Reviewed by chapuni. Sorry for breaking.

llvm-svn: 133200

llvm-svn: 133189

than trying to insert them immediately after the invoke.

llvm-svn: 133188

llvm-svn: 133176

llvm-svn: 133172

names for named metadata nodes.

llvm-svn: 133166

Original patch by Syoyo Fujita with more comments by me.

llvm-svn: 133153

llvm-svn: 133139

llvm-svn: 133134

llvm-svn: 133133

llvm-svn: 133132

REQUIRES: Asserts
REQUIRES: Debug

This required chaining test configuration properties. It seems like a
generally good thing to do.

llvm-svn: 133131

llvm-svn: 133128

accumulator forwarding.  Specifically (from SVN log entry):

Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2

Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was
intended in the original revision.

llvm-svn: 133127

llvm-svn: 133124

llvm-svn: 133115

Function::getNumBlockIDs() should be used instead of Function::size() to set the upper limit on the block IDs since basic blocks might get removed (simplified away) after being initially numbered. Plus the test case, in which SelectionDAGBuilder::visitBr() calls llvm::MachineFunction::removeFromMBBNumbering(), which introduces the hole in numbering leading to an assert in llc (prior to the fix).

llvm-svn: 133113

llvm-svn: 133108

llvm-svn: 133089

optimizations when emitting calls to the function;  instead those calls may
use faster relocations which require the function to be immediately resolved
upon loading the dynamic object featuring the call.  This is useful when it
is known that the function will be called frequently and pervasively and
therefore there is no merit in delaying binding of the function.

Currently only implemented for x86-64, where it turns into a call through
the global offset table.

Patch by Dan Gohman, who assures me that he's going to add LangRef documentation
for this once it's committed.

llvm-svn: 133080

llvm-svn: 133068

Note that this actually changes code generation, and someone who
understands this target better should check the changes.

- R12Q is now allocatable. I think it was omitted from the allocation
  order by mistake since it isn't reserved. It as apparently used as a
  GOT pointer sometimes, and it should probably be reserved if that is
  the case.

- The GR64 registers are allocated in a different order now. The
  register allocator will automatically put the CSRs last. There were
  other changes to the order that may have been significant.

The test fix is because r0 and r1 swapped places in the allocation order.

llvm-svn: 133067

llvm-svn: 133064

Added a test case for handling physreg aliases during pre-RA-sched.

llvm-svn: 133063