Commits · 61c1bd5abcc6f6c20ec9835f96aa2500452b16e5 · Lorenzo Albano / LLVM bpEVL · GitLab

Jul 27, 2017
- [InlineCost, NFC] Change CallAnalyzer::isGEPFree to use TTI::getUserCost instead of TTI::getGEPCost · 61c1bd5a
  Evgeny Astigeevich authored Jul 27, 2017
  61c1bd5a
- Re-commit: r309094 [globalisel][tablegen] Fuse the generated tables together. · 8e82af2b
  Daniel Sanders authored Jul 27, 2017
  8e82af2b
- [X86] Tidyup MaskedLoad/Store mask creation. NFCI. · afc1ac27
  Simon Pilgrim authored Jul 27, 2017
  afc1ac27
- [TTI] fixing a bug in the isLegalMaskedScatter API · cef53dcb
  Mohammed Agabaria authored Jul 27, 2017
  cef53dcb
- [PowerPC] enable optimizeCompareInstr for branch with static branch hint · 967dc58a
  Hiroshi Inoue authored Jul 27, 2017
  967dc58a
- [X86] Improve the unknown stepping support for Intel CPUs in getHostCPUName · 4eda7561
  Craig Topper authored Jul 27, 2017
  4eda7561
- [DWARF] Minor code style modification, no functionality change. · 73e1796d
  Spyridoula Gravani authored Jul 27, 2017
  73e1796d
- DebugInfo: Ensure imported entities at the top level of an inlined function... · 2195e136
  David Blaikie authored Jul 27, 2017
  2195e136
- [Hexagon] Fix expensive checks build bot broken in r309230. · 569932d1
  Eugene Zelenko authored Jul 26, 2017
  569932d1
- [Hexagon] Partially revert r309230 which caused some build bots failures. · efd3d588
  Eugene Zelenko authored Jul 26, 2017
  efd3d588
- [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use... · e4fc6ee7
  Eugene Zelenko authored Jul 26, 2017
  e4fc6ee7
Jul 26, 2017
- Fix a comment (test commit). · 0445e31c
  Hiroshi Yamauchi authored Jul 26, 2017
  0445e31c
- [AMDGPU] Optimize SI_IF lowering for simple if regions · 3197eb69
  Stanislav Mekhanoshin authored Jul 26, 2017
  3197eb69
- [ARM] Minor cosmetic edits (NFC) · b3ed4bcb
  Evandro Menezes authored Jul 26, 2017
  b3ed4bcb
- [AArch64] Adjust the cost model for Exynos M1 and M2 · d192a8ae
  Evandro Menezes authored Jul 26, 2017
  d192a8ae
- AMDGPU : Widen extending scalar loads to 32-bits. · a126a13b
  Wei Ding authored Jul 26, 2017
  a126a13b
- AMDGPU: Fix using SMRD instructions for argument loads in functions · 894e53d6
  Matt Arsenault authored Jul 26, 2017
  894e53d6
- AMDGPU/GlobalISel: Mark 32-bit G_OR as legal · 55038cd1
  Tom Stellard authored Jul 26, 2017
  55038cd1
- Change CallLoweringInfo::CS to be an ImmutableCallSite instead of a pointer. NFCI. · 081ffe2f
  Peter Collingbourne authored Jul 26, 2017
  081ffe2f
- Migrate SimplifyLibCalls to new OptimizationRemarkEmitter · ea06e6e8
  Adam Nemet authored Jul 26, 2017
  ea06e6e8
- This patch returns proper value to indicate the case when instruction... · d1fefa3d
  Andrew V. Tischenko authored Jul 26, 2017
  d1fefa3d
- Do a better job at emitting prefrabricated skeleton CUs. · 833ad37c
  Adrian Prantl authored Jul 26, 2017
  833ad37c
- Unlink nodes instead of copying, to avoid memory problems. · 6ba5c813
  Eric Beckmann authored Jul 26, 2017
  6ba5c813
- [Dominators] Move root-finding out of DomTreeBase and simplify it · c271dea0
  Jakub Kuderski authored Jul 26, 2017
  c271dea0
- Simplify. NFC. · e06e4df8
  Rafael Espindola authored Jul 26, 2017
  e06e4df8
- [Hexagon] Mark raise_relocation_error as NORETURN. · 239e4b93
  Florian Hahn authored Jul 26, 2017
  239e4b93
- Update the assertion to meet with the changes in r309121. (NFC) · 641f387c
  Dehao Chen authored Jul 26, 2017
  641f387c
- Make new PM honor -fdebug-info-for-profiling · e90d0153
  Dehao Chen authored Jul 26, 2017
  e90d0153
- [NFC] test commit. · df0ee9e1
  Stefan Pintilie authored Jul 26, 2017
  df0ee9e1
- [Bash-autocompletion] Show HelpText with possible flags · 66256906
  Yuka Takahashi authored Jul 26, 2017
  66256906
- DAGCombiner: Extend reduceBuildVecToTrunc to handle non-zero offset · 092f1991
  Zvi Rackover authored Jul 26, 2017
  092f1991
- [COFF, ARM64] Fix symbol offsets in ADRP/ADD/LDR/STR relocations · 0b7bf7a2
  Martin Storsjö authored Jul 26, 2017
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- [ARM] GlobalISel: Map G_GLOBAL_VALUE to GPR · a5d6518e
  Diana Picus authored Jul 26, 2017
  a5d6518e
- [ARM] GlobalISel: Mark G_GLOBAL_VALUE as legal · b1fd7849
  Diana Picus authored Jul 26, 2017
  b1fd7849
- [libOption] - Add flag allowing to print options aliases in help text. · 4530dffb
  George Rimar authored Jul 26, 2017
  4530dffb
- [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess. · c1918ad5
  Michael Zuckerman authored Jul 26, 2017
  c1918ad5
- TargetLowering: Change isShuffleMaskLegal's mask argument type to ArrayRef<int>. NFCI. · 1b736822
  Zvi Rackover authored Jul 26, 2017
  1b736822
- [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess part1. · 60bc7e0f
  Michael Zuckerman authored Jul 26, 2017
  60bc7e0f
- [SCEV] Cache results of computeExitLimit · f282aed4
  Max Kazantsev authored Jul 26, 2017
  f282aed4
- [X86] Prevent selecting masked aligned load instructions if the load should be non-temporal · 050c9c8f
  Craig Topper authored Jul 26, 2017
  050c9c8f