Legalize and emit code for:

  * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word
  * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word

Differential Revision: https://reviews.llvm.org/D45635

llvm-svn: 331790

llvm-svn: 331789

Reviewer: Nicolai

Differential Revision:
  https://reviews.llvm.org/D46438

llvm-svn: 331788

Legalize and emit code for:

  * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword
  * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword

Differential Revision: https://reviews.llvm.org/D45553

llvm-svn: 331787

Differential Revision: https://reviews.llvm.org/D46514
Patch by Nikolai Kosjar.

llvm-svn: 331786

Remap on reserve of more than the current size.
Don't remap on downsize.

llvm-svn: 331784

CodeGenPrepare pass move extension instructions close to load instructions in different BB, so they can be combined later. But the extension instructions can't move through logical and shift instructions in current implementation. This patch enables this enhancement, so we can eliminate more extension instructions.

Differential Revision: https://reviews.llvm.org/D45537

llvm-svn: 331783

This change makes it explicit that the main loop iterates over a
parallel array, Syms and ObjSyms.

llvm-svn: 331780

llvm-svn: 331779

Existing DAG combine only handles conversions for FP_TO_SINT:
"{f32, f64} x { i32, i16 }"

This patch simplifies the code to handle:
"{ FP_TO_SINT, FP_TO_UINT } x { f64, f32 } x { i64, i32, i16, i8 }"

Differential Revision: https://reviews.llvm.org/D46102

llvm-svn: 331778

In an effort to make the .debug_types patch smaller, breaking out the part that reads the .debug_types from object files into a separate patch

Differential Revision: https://reviews.llvm.org/D46529

llvm-svn: 331777

Set the exit code to 1 if no arguments are specified.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D46547

llvm-svn: 331776

- Report error for invalid dpp_ctrl values.
- Changed the way it is reported, now the error will be emitted into
  asm and will work with release build as well.
- Added dpp_ctrl value verifier for codegen.
- Added symbolic constants for dpp_ctrl.

Differential Revision: https://reviews.llvm.org/D46565

llvm-svn: 331775

llvm-svn: 331774

llvm-svn: 331773

Some MIPS relocations depend on "gp" value. By default, this value has
0x7ff0 offset from a .got section. But relocatable files produced by a
compiler or a linker might redefine this default value and we have to
use it for a calculation of the relocation result. When we generate EXE
or DSO it's trivial. Generating a relocatable output is more difficult
case because the linker does calculate relocations in this case and
cannot store individual "gp" values used by each input object file.
As a workaround we add the "gp" value to the relocation addend.

This fixes https://llvm.org/pr31149

Differential revision: https://reviews.llvm.org/D45972

llvm-svn: 331772

Introduced a new pattern for matching splat.d explicitly.

Both splat.d and splati.d can now be generated from the @llvm.mips.splat.d
intrinsic depending on whether an immediate value has been passed.

Differential Revision: https://reviews.llvm.org/D45683

llvm-svn: 331771

This fixes a couple of BtVer2 missing instructions that weren't been handled in the override.

NOTE: There are still a lot of overrides that still need cleaning up!
llvm-svn: 331770

llvm-svn: 331769

The linkage of the global entries must be weak to enable support of
redefinition of the same target regions in multiple compilation units.

llvm-svn: 331768

I've created the necessary classes but there are still a lot of overrides that need cleaning up.

NOTE: The Znver1 model was missing some div/idiv variants in the instregex patterns and wasn't setting the resource cycles at all in the overrides.
llvm-svn: 331767

Generate a printable OpenCL language version number in a single place
and select between the OpenCL C or OpenCL C++ version accordingly.

Differential Revision: https://reviews.llvm.org/D46382

llvm-svn: 331766

llvm-svn: 331765

Re-enable TestUnicodeSymbols now that we use the in-tree dsymutil. This
was disabled because the hashing of unicode symbols was out of sync
between llvm (dsymutil) and lldb.

llvm-svn: 331764

Summary:
As discussed in D45931, currently, profiling output of clang-tidy is somewhat not great.
It outputs one profile at the end of the execution, and that profile contains the data
from the last TU that was processed. So if the tool run on multiple TU's, the data is
not accumulated, it is simply discarded.

It would be nice to improve this.

This differential is the first step - make this profiling info per-TU,
and output it after the tool has finished processing each TU.
In particular, when `ClangTidyASTConsumer` destructor runs.

Next step will be to add a CSV (JSON?) printer to store said profiles under user-specified directory prefix.

Reviewers: alexfh, sbenza

Reviewed By: alexfh

Subscribers: Eugene.Zelenko, mgorny, xazax.hun, mgrang, klimek, cfe-commits

Tags: #clang-tools-extra

Differential Revision: https://reviews.llvm.org/D46504

llvm-svn: 331763

Patch by Rafael Stahl!

Differential Revision: https://reviews.llvm.org/D46115

llvm-svn: 331762

The tokenizer handles comments since SVN r315207.

llvm-svn: 331761

Split off from existing vector load/store classes to remove InstRW overrides.

llvm-svn: 331760

Differential Revision: https://reviews.llvm.org/D46233

llvm-svn: 331759

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D46251

llvm-svn: 331758

Split off from SchedWriteVecLogic to remove InstRW overrides.

llvm-svn: 331757

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46388

llvm-svn: 331756

Patch https://reviews.llvm.org/D41445 changed the behaviour of 'isReg()'
to also return 'true' if the parsed register operand is a vector
register. Code in the AsmMatcher checks if a register is a subclass of the
expected register class. However, even though both parsed registers map
to the same physical register, the 'v' register is of kind 'NeonVector',
where 'q' is of type Scalar, where isSubclass() does not distinguish
between the two cases.

The solution is to use an AsmOperand instead of the register directly,
and use the PredicateMethod to distinguish the two operands.

This fixes for example:
  ldr v0, [x0]    // 'v0' is an invalid operand for this instruction
  ldr q0, [x0]    // valid

Reviewers: aemerson, Gerolf, SjoerdMeijer, javed.absar

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D46310

llvm-svn: 331755

Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D46125

llvm-svn: 331754

llvm-svn: 331753

In the recognise test convert some ST1 multiple structure to ST1 single
structure to test the isST1SingleOpcode() function.

Differential Revision: https://reviews.llvm.org/D46263

llvm-svn: 331752

Add two test cases to improve the code coverage of ThunkSection creation
when there are no existing ThunkSections in range. There are two test
cases, one where a new section can be created and another to trigger the
"InputSection too large for range extension thunk" error message. A recent
code coverage report showed that this section of code wasn't covered by a
test case.

Differential Revision: https://reviews.llvm.org/D46261

llvm-svn: 331751

Reviewers: hans

Reviewed By: hans

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D46572

llvm-svn: 331750

This is a fix for PR30290: by marking all byval stack slots as being aliased,
the instruction scheduler is more conservative about rescheduling memory
accesses to such stack slots as an LLVM Value* might alias it. This fixes
errors such as in the patched test case, where reads and writes to a data
structure are illegally mixed.

This could be fixed better in the future with better analysis for the
instruction scheduler to know what Values alias what stack slots.

Differential Revision: https://reviews.llvm.org/D45022

llvm-svn: 331749

This patch adds a shadow stack fix when compiling
setjmp/longjmp with the shadow stack enabled. This
allows setjmp/longjmp to work correctly with CET.

Patch by mike.dvoretsky

Differential Revision: https://reviews.llvm.org/D46181

llvm-svn: 331748