Commits · 669bb3111ff0b4b300a2218b88ad71f8e58bebb7 · Lorenzo Albano / LLVM bpEVL · GitLab

Jun 30, 2020
- Mips: Don't store MachineFunction in MipsFunctionInfo · 669bb311
  Matt Arsenault authored Jun 18, 2020
  669bb311
- [IR] Delete llvm::Constants using the correct type. · 15440191
  Eli Friedman authored Jun 24, 2020
  15440191
- [AArch64] Add getCFInstrCost, treat branches as free for throughput. · 1ccc4992
  Florian Hahn authored Jun 30, 2020
  1ccc4992
- [X86] Move frontend CPU feature initialization to a look up table based implementation. NFCI · 3537939c
  Craig Topper authored Jun 30, 2020
  3537939c
- [InstCombine] fma x, y, 0 -> fmul x, y · 9e49d1d9
  David Green authored Jun 30, 2020
  9e49d1d9
- [openmp] Move Directive and Clause helper function to tablegen · 1a70077b
  Valentin Clement authored Jun 30, 2020
  1a70077b
- [macho] emit LC_BUILD_VERSION load command for supported OSes and platforms · 24a1447b
  Alex Lorenz authored Jun 29, 2020
  24a1447b
- [PDB] Defer public serialization until PDB writing · b7402edc
  Reid Kleckner authored Jun 04, 2020
  b7402edc
- [SVE] Remove calls to VectorType::getNumElements from AArch64 · ab35ba57
  Christopher Tetreault authored Jun 30, 2020
  ab35ba57
- [SVE] Remove calls to VectorType::getNumElements from ExecutionEngine · 9b500e56
  Christopher Tetreault authored Jun 30, 2020
  9b500e56
- [MVT] Add new MVT types for RISC-V vector. · a7b0f391
  Hsiangkai Wang authored Jun 12, 2020
  a7b0f391
- [ARM] Allow the fabs intrinsic to be tail predicated · 3324e3a6
  Samuel Tebbs authored Jun 30, 2020
  3324e3a6
- Pass MDFieldPrinter::printAPInt APInt arg by reference not value. · 32f8cd9a
  Simon Pilgrim authored Jun 30, 2020
  32f8cd9a
- [ARM] Allow the usub_sat and ssub_sat intrinsics to be tail predicated · 66fa3139
  Samuel Tebbs authored Jun 30, 2020
  66fa3139
- RegAlloc: Start using Register · b7f6ecf0
  Matt Arsenault authored Jun 30, 2020
  
  b7f6ecf0
- BranchFolding: Use Register · af1eeaf3
  Matt Arsenault authored Jun 30, 2020
  
  af1eeaf3
- TailDuplicator: Use Register · edb4a5cb
  Matt Arsenault authored Jun 30, 2020
  
  edb4a5cb
- AMDGPU: Use Register · cac655f2
  Matt Arsenault authored Jun 23, 2020
  
  cac655f2
- X86: Use Register · 249933f2
  Matt Arsenault authored Jun 28, 2020
  
  249933f2
- [ARM][MVE] Tail-predication: clean-up of unused code · af459076
  Sjoerd Meijer authored Jun 29, 2020
  af459076
- [ARM] Allow rounding intrinsics to be tail predicated · d9cb811c
  Samuel Tebbs authored Jun 30, 2020
  d9cb811c
- [Alignment][NFC] TargetLowering::allowsMemoryAccessForAlignment · 423458ec
  Guillaume Chatelet authored Jun 30, 2020
  423458ec
- [X86][SSE] LowerVectorAllZero - add support for masked OR-reductions · 82de0189
  Simon Pilgrim authored Jun 30, 2020
  82de0189
- [Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemcpy to Align · c1cd61e0
  Guillaume Chatelet authored Jun 30, 2020
  c1cd61e0
- [Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemmove to Align · 306d7c69
  Guillaume Chatelet authored Jun 30, 2020
  306d7c69
- [Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemset to Align · 6a6af30d
  Guillaume Chatelet authored Jun 30, 2020
  6a6af30d
- [PM] Fix new PM to perform SpeculativeExecution as in old PM · 1a6cebb4
  dfukalov authored Jun 29, 2020
  1a6cebb4
- [SystemZ] Add NoMerge MIFlag · 67648695
  Ilya Leoshkevich authored Jun 30, 2020
  67648695
- [llvm][Z3][NFC] Improve mkBitvector performance · 815a8100
  Balazs Benics authored Jun 30, 2020
  815a8100
- [Alignment][NFC] Migrate AtomicExpandPass to Align · 2c5ff48e
  Guillaume Chatelet authored Jun 30, 2020
  2c5ff48e
- [yaml2obj] - Support reading a content as an array of bytes using the new 'ContentArray' key. · 64bae035
  Georgii Rymar authored Jun 23, 2020
  64bae035
- AMDGPU/GlobalISel: Select icmp intrinsic · d7173826
  Petar Avramovic authored Jun 30, 2020
  d7173826
- [GlobalISel][InlineAsm] Add support for matching input constraints · 4b980cc9
  Petar Avramovic authored Jun 30, 2020
  4b980cc9
- [DWARFYAML][debug_info] Replace 'InitialLength' with 'Format' and 'Length'. · fe08ab54
  Xing GUO authored Jun 30, 2020
  fe08ab54
- [Alignment][NFC] TargetLowering::allowsMemoryAccess · 5f8bdb3e
  Guillaume Chatelet authored Jun 30, 2020
  5f8bdb3e
- [Alignment][NFC] Migrate PPC, X86 and XCore backends to Align · a976ea32
  Guillaume Chatelet authored Jun 30, 2020
  a976ea32
- [MSP430] Declare comparison LibCalls as returning i16 instead of i32 · 19e75717
  Anatoly Trosinenko authored Jun 30, 2020
  19e75717
- [Alignment][NFC] Migrate AArch64, ARM, Hexagon, MSP and NVPTX backends to Align · 4f5133a4
  Guillaume Chatelet authored Jun 30, 2020
  4f5133a4
- [X86] Remove an isel pattern than can never match. Remove bitcasts of loads from a few others. · 767c9c5b
  Craig Topper authored Jun 30, 2020
  
  767c9c5b
- [CodeGen] Fix warning in getNode for EXTRACT_SUBVECTOR · c02332a6
  David Sherwood authored Jun 29, 2020
  c02332a6