Document memory attached last level (MALL) cache added in GFX10.3.

Reviewed By: t-tye

Differential Revision: https://reviews.llvm.org/D114076

It should be semantically identical if it was set to the same value as
the default. Also improve the documentation.

Document the CSR AGPRs for GFX90A.

Remove the TODO for gfx908, as the answer is that we don't mark any
AGPRs as callee-saved except for GFX90A, i.e. the docs as-is are correct
for gfx908.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D109009

Switch to using BitIntegerState for each of the inputs, and invert
their meanings.

This now diverges more from the old AMDGPUAnnotateKernelFeatures, but
this isn't used yet anyway.

Reviewed By: xgupta

Differential Revision: https://reviews.llvm.org/D108557

This patch introduces a new code object metadata field, ".kind"
which is used to add support for init and fini kernels.

HSAStreamer will use function attributes, "device-init" and
"device-fini" to distinguish between init and fini kernels from
the regular kernels and will emit metadata with ".kind" set to
"init" and "fini" respectively.

To reduce the number of init and fini kernels, the ctors and
dtors present in the llvm's global.ctors and global.dtors lists
are called from a single init and fini kernel respectively.

Reviewed by: yaxunl

Differential Revision: https://reviews.llvm.org/D105682

This reverts commit d42e70b3.

This patch introduces a new code object metadata field, ".kind"
which is used to add support for init and fini kernels.

HSAStreamer will use function attributes, "device-init" and
"device-fini" to distinguish between init and fini kernels from
the regular kernels and will emit metadata with ".kind" set to
"init" and "fini" respectively.

To reduce the number of init and fini kernels, the ctors and
dtors present in the llvm's global.ctors and global.dtors lists
are called from a single init and fini kernel respectively.

Reviewed by: yaxunl

Differential Revision: https://reviews.llvm.org/D105682

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D106249

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D106034

Currently, if target of s_branch instruction is in another section, it will fail with the error of undefined label.  Although in this case, the label is not undefined but present in another section. This patch tries to handle this issue. So while handling fixup_si_sopp_br fixup in getRelocType, if the target label is undefined we issue an error as before. If it is defined, a new relocation type R_AMDGPU_REL16 is returned.

This issue has been reported in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100181 and https://bugs.llvm.org/show_bug.cgi?id=45887. Before https://reviews.llvm.org/D79943, we used to get an crash for this scenario. The crash is fixed now but the we still get an undefined label error.  Jumps to other section can arise with hold/cold splitting.

A patch to handle the relocation in lld will follow shortly.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D105760

Reviewed By: xgupta

Differential Revision: https://reviews.llvm.org/D105825

The documentation for the AMDGPU assembler's examples don't show the
.args section, which, if ommitted, will cause arguments to silently
not be passed into the kernel. This commit fixes this issue.

Reviewed By: #amdgpu, scott.linder

Differential Revision: https://reviews.llvm.org/D105222

Reviewed By: kzhuravl

Differential Revision: https://reviews.llvm.org/D105377

Set informational fields in the .shader_functions table.

Also correct the documentation, .scratch_memory_size and .lds_size are
integers.

Differential Revision: https://reviews.llvm.org/D105116

Update AMDGPU gfx90a memory model to make coarse grain memory allocations
consistent when fine grained system scope atomic acquire and release is
performed.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D105137

Reviewed By: kzhuravl, rampitec

Differential Revision: https://reviews.llvm.org/D104872

Differential Revision: https://reviews.llvm.org/D104804

This reverts commit 211e584f.

Fixed a use-after-free error that caused the sanitizers to fail.

This reverts commit ea10a869.

A sanitizer buildbot reports an error.

Differential Revision: https://reviews.llvm.org/D103663

Add link to documentation for "AMD Instinct MI100 Instruction Set
Architecture" to AMDGPUUsage.rst.

Reviewed By: kzhuravl, rampitec, dp

Differential Revision: https://reviews.llvm.org/D102859

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D102910

Add support for the readonly flat Scratch register initialized
by the SPI.

Differential Revision: https://reviews.llvm.org/D102432

Summary of changes:
- added description of GFX90A;
- minor bugfixing and improvements.

Differential Revision: https://reviews.llvm.org/D102306

The product name for gfx908 is "AMD Instinct MI100 Accelerator".

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D102209

Differential Revision: https://reviews.llvm.org/D100126

Correct indentation that results in rST syntax error.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D100070

Reviewed By: msearles

Differential Revision: https://reviews.llvm.org/D99781

Change-Id: I65f3edcfe5063551cad5aab0da1374c3a6ccd3a2

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D99223

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D99196

Reserve AMD GPU ELF machine code 0x040.

Minor AMDGPUUsage format consistency change.

Reviewed By: kzhuravl

Differential Revision: https://reviews.llvm.org/D99122

Document the default for the XNACK and SRAMECC target features for code object V2-V3 and V4.

Reviewed By: kzhuravl

Differential Revision: https://reviews.llvm.org/D97598

  - Sort MACHs by its value
  - Add missing reserved MACHs
    - EF_AMDGPU_MACH_AMDGCN_RESERVED_0X3D
    - EF_AMDGPU_MACH_AMDGCN_RESERVED_0X3E

Differential Revision: https://reviews.llvm.org/D97010