Commits · 712d1557a2befcdc5635fedbb6eb308f8cda2929 · Lorenzo Albano / LLVM bpEVL · GitLab

Jun 11, 2014
- Remove support for runtime multi-threading. · f6054ca1
  Zachary Turner authored Jun 10, 2014
  f6054ca1
- Move AArch64InstrInfo to AArch64Subtarget. · f63bc64d
  Eric Christopher authored Jun 10, 2014
  f63bc64d
- Remove a method that was just replacing direct access to a member. · 58f32667
  Eric Christopher authored Jun 10, 2014
  58f32667
- Remove the use of TargetMachine from X86InstrInfo. · 6c786a1d
  Eric Christopher authored Jun 10, 2014
  6c786a1d
- Move X86RegisterInfo away from using the TargetMachine and only · 1f8ad4f4
  Eric Christopher authored Jun 10, 2014
  1f8ad4f4
Jun 10, 2014
- Mark a few functions noexcept. · f5d07fa5
  Rafael Espindola authored Jun 10, 2014
  f5d07fa5
- Use the TargetMachine on the DAG or the MachineFunction instead · 68d7559e
  Eric Christopher authored Jun 10, 2014
  68d7559e
- R600/SI: Emit an error when attempting to spill VGPRs v4 · 4e07b1d7
  Tom Stellard authored Jun 10, 2014
  4e07b1d7
- R600/SI: Fix a crash when spilling SGPRs · 060ae390
  Tom Stellard authored Jun 10, 2014
  060ae390
- We already have a reference to the TargetMachine, use that. · 2af33756
  Eric Christopher authored Jun 10, 2014
  2af33756
- Have isInTailCallPosition take the DAG so that we can use the · 576d36ae
  Eric Christopher authored Jun 10, 2014
  576d36ae
- Reorder includes to be sorted. · 09fc276d
  Eric Christopher authored Jun 10, 2014
  09fc276d
- Revert "Patch by Ray Donnelly to print register names instead of numbers." · b01961c2
  Reid Kleckner authored Jun 10, 2014
  b01961c2
- Fix error in tablegen when either operand of !if is an empty list. · a73fd935
  Matt Arsenault authored Jun 10, 2014
  a73fd935
- Fix typos. · db5028bd
  Eric Christopher authored Jun 10, 2014
  db5028bd
- R600: Use BCNT_INT for evergreen · 6042506b
  Matt Arsenault authored Jun 10, 2014
  6042506b
- R600/SI: Implement i64 ctpop · 8333e437
  Matt Arsenault authored Jun 10, 2014
  8333e437
- R600/SI: Use bcnt instruction for ctpop · b5b5110b
  Matt Arsenault authored Jun 10, 2014
  b5b5110b
- R600: Handle fcopysign · 6e43965f
  Matt Arsenault authored Jun 10, 2014
  6e43965f
- R600/SI: Handle sign_extend and zero_extend to i64 with patterns. · b2cbf799
  Matt Arsenault authored Jun 10, 2014
  b2cbf799
- Add a FIXME. · 19b1d73e
  Eric Christopher authored Jun 10, 2014
  19b1d73e
- Move AArch64SelectionDAGInfo down to the subtarget. · fcb06ca9
  Eric Christopher authored Jun 10, 2014
  fcb06ca9
- [FastISel] Collect statistics about failing intrinsic calls. · 89fe23e8
  Juergen Ributzka authored Jun 10, 2014
  89fe23e8
- Remove the cached little endian variable. We can get it easily off · 17254eea
  Eric Christopher authored Jun 10, 2014
  17254eea
- Have AArch64SelectionDAGInfo take a DataLayout parameter rather · 078a2b62
  Eric Christopher authored Jun 10, 2014
  078a2b62
- Remove caching of the subtarget for AArch64SelectionDAGInfo. · 57c2319b
  Eric Christopher authored Jun 10, 2014
  57c2319b
- Move DataLayout onto the AArch64 subtarget. · 6f2a203f
  Eric Christopher authored Jun 10, 2014
  6f2a203f
- Test commit, wraps some lines to fit in 80 columns. · a40ccf62
  Zachary Turner authored Jun 10, 2014
  a40ccf62
- Move AArch64FrameLowering into the subtarget. · 29aab7b3
  Eric Christopher authored Jun 10, 2014
  29aab7b3
- Remove the uses of AArch64TargetMachine and AArch64Subtarget from · bc76b977
  Eric Christopher authored Jun 10, 2014
  bc76b977
- Do Materialize Floating Point in Mips Fast-Isel · 063d4fba
  Reed Kotler authored Jun 10, 2014
  063d4fba
- [X86] Improved target combine rules for selecting horizontal add/sub. · fa508af0
  Andrea Di Biagio authored Jun 10, 2014
  fa508af0
- Hexagon: Expand i1 SELECT_CC · d172270c
  Tom Stellard authored Jun 10, 2014
  d172270c
- [X86] AVX512: Add vmovntdqa · 7f62b23e
  Adam Nemet authored Jun 10, 2014
  7f62b23e
- Fix a bug in the Thumb1 ARM Load/Store optimizer · 65eea557
  Renato Golin authored Jun 10, 2014
  65eea557
- SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CC · 3787b122
  Tom Stellard authored Jun 10, 2014
  3787b122
- SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors · b9a02338
  Tom Stellard authored Jun 10, 2014
  b9a02338
- SelectionDAG: Expand SELECT_CC to SELECT + SETCC · 3ca1bfc7
  Tom Stellard authored Jun 10, 2014
  3ca1bfc7
- [PPC64LE] Recognize shufflevector patterns for little endian · f910a065
  Bill Schmidt authored Jun 10, 2014
  f910a065
- [AArch64] Emit .ident compiler version attribute. · d863ae39
  Chad Rosier authored Jun 10, 2014
  d863ae39