llvm-svn: 15710

SparcV9 and PowerPC64 without target triples, since they are both 64-bit
big-endian targets.

llvm-svn: 15688

* BuildMI() can build 0-param instructions (e.g., NOP)

llvm-svn: 15681

* BuildMI() really *does* handle 0 params!

llvm-svn: 15680

* Fix loading of GlobalValues

llvm-svn: 15678

llvm-svn: 15677

llvm-svn: 15674

llvm-svn: 15673

* Mark InstrInfo with 32 vs. 64 bit flag
* Enable the 64-bit isel and asm printer

llvm-svn: 15672

llvm-svn: 15671

* Doubles are 8 bytes in 64-bit PowerPC, and use the general register class
* Use double-word loads and stores for restoring from/saving to stack
* Do not allocate R2 if compiling for AIX

llvm-svn: 15670

llvm-svn: 15669

llvm-svn: 15668

llvm-svn: 15667

llvm-svn: 15665

llvm-svn: 15663

llvm-svn: 15662

llvm-svn: 15661

llvm-svn: 15648

llvm-svn: 15636

llvm-svn: 15635

llvm-svn: 15634

llvm-svn: 15631

* Wrap long line to 80 cols

llvm-svn: 15630

Replace STDX (store 64 bit int indexed) with STFDX (store double indexed)
Fix latent bug in indexed load generation
Generate indexed loads and stores in many more cases

llvm-svn: 15626

llvm-svn: 15620

llvm-svn: 15613

llvm-svn: 15600

llvm-svn: 15599

llvm-svn: 15586

llvm-svn: 15580

llvm-svn: 15578

llvm-svn: 15577

push onto the top of the stack like x86, which uses the local area
offset.  This will allow the removal of PowerPCPEI.cpp soon.

llvm-svn: 15573

Changes commited for Nate Begeman:

Use a PowerPC specific prolog epilog inserter to control where spilled
callee save regs are placed on the stack.
Get rid of implicit return address stack slot, save return address reg
(LR) in appropriate slot
Improve code generated for functions that don't have calls or access
globals


Note from Chris: PowerPCPEI will eventually be eliminated, once the
functionality is merged into CodeGen/PrologEpilogInserter.cpp

llvm-svn: 15536

assume Louis also holds copyright.

llvm-svn: 15534

Thanks Nate!

llvm-svn: 15531

llvm-svn: 15527

llvm-svn: 15504

llvm-svn: 15501