Commits · 7bfec3e78698185dd4abc463e7c5ec17ee8550ba · Lorenzo Albano / LLVM bpEVL · GitLab

Feb 14, 2013
- AArch64: stop claiming that NEON registers are usable for now. · d21ddb90
  Tim Northover authored Feb 14, 2013
  d21ddb90
- AArch64: add block comments where missing · 75f436c4
  Tim Northover authored Feb 14, 2013
  75f436c4
- Make ARMAsmParser accept the correct alignment specifier syntax in instructions. · 2efb59a7
  Kristof Beyls authored Feb 14, 2013
  2efb59a7
- Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure). · d0a0cc80
  Elena Demikhovsky authored Feb 14, 2013
  d0a0cc80
- R600/SI: Check for empty stack in SIAnnotateControlFlow::isTopOfStack · ae0a403d
  Michel Danzer authored Feb 14, 2013
  ae0a403d
- Revert r175120 and r175121. Clang is producing the expected asm names again. · 8868faac
  Rafael Espindola authored Feb 14, 2013
  8868faac
- Remove the form field from Mips16 instruction formats and set things · ec8a5490
  Reed Kotler authored Feb 14, 2013
  ec8a5490
- Don't assume the mangling of static functions. · 3c818086
  Rafael Espindola authored Feb 14, 2013
  3c818086
- Don't asume that a static function in an extern "C" block will not be mangled. · 76499349
  Rafael Espindola authored Feb 14, 2013
  76499349
- temporarily revert the patch due to some conflicts · 090edf7e
  Weiming Zhao authored Feb 13, 2013
  090edf7e
Feb 13, 2013
- Hexagon: add support for predicate-GPR copies. · e96f804e
  Anshuman Dasgupta authored Feb 13, 2013
  e96f804e
- R600: Add support for 128-bit parameters · 91da4e91
  Tom Stellard authored Feb 13, 2013
  91da4e91
- Don't build tail calls to functions with three inreg arguments on x86-32 PIC. · beba9726
  Nick Lewycky authored Feb 13, 2013
  beba9726
- Bug fix 13622: Add paired register support for inline asm with 64-bit data on ARM · 0632a4b0
  Weiming Zhao authored Feb 13, 2013
  0632a4b0
- Hexagon: Use absolute addressing mode loads/stores for global+offset · d9225246
  Jyotsna Verma authored Feb 13, 2013
  d9225246
- [ms-inline-asm] Add support for memory references that have non-immediate · 282edd7c
  Chad Rosier authored Feb 13, 2013
  282edd7c
- For Mips 16, add the optimization where the 16 bit form of addiu sp can be used · f662cff6
  Reed Kotler authored Feb 13, 2013
  f662cff6
- MIsched: HazardRecognizers are created for each DAG. Free them. · 553e0fe3
  Andrew Trick authored Feb 13, 2013
  553e0fe3
- Add registration for PPC-specific passes to allow the IR to be dumped · 2680b53d
  Krzysztof Parzyszek authored Feb 13, 2013
  2680b53d
- X86: Disable generation of rep;movsl when %esi is used as a base pointer. · 8e2637e2
  Benjamin Kramer authored Feb 13, 2013
  8e2637e2
- Make jumptables work for -static · 9cb8e7b9
  Reed Kotler authored Feb 13, 2013
  9cb8e7b9
- Prevent insertion of "vzeroupper" before call that preserves YMM registers,... · 9e0df7cb
  Elena Demikhovsky authored Feb 13, 2013
  9e0df7cb
- Check i1 as well as i8 variables for 8 bit registers for x86 inline · 389ee71b
  Eric Christopher authored Feb 13, 2013
  389ee71b
- Test commit. Fixed typo. · 4299cf83
  David Peixotto authored Feb 13, 2013
  4299cf83
Feb 12, 2013
- Hexagon: Add support to generate predicated absolute addressing mode · 39f7a2b7
  Jyotsna Verma authored Feb 12, 2013
  39f7a2b7
- [NVPTX] Disable vector registers · be8dc649
  Justin Holewinski authored Feb 12, 2013
  be8dc649
- R600: Fix regression with shadow array sampler on pre-SI GPUs. · 3bb17ebd
  Michel Danzer authored Feb 12, 2013
  3bb17ebd
- ARM cost model: Add vector reverse shuffle costs · 89aef938
  Arnold Schwaighofer authored Feb 12, 2013
  89aef938
- ARM NEON: Handle v16i8 and v8i16 reverse shuffles · 1f3d3ca7
  Arnold Schwaighofer authored Feb 12, 2013
  1f3d3ca7
- Added 0x0D to 2-byte opcode extension table for prefetch* variants · ab588efe
  Kay Tiong Khoo authored Feb 12, 2013
  ab588efe
Feb 11, 2013
- [mips] Expand pseudo instructions before they are emitted in · bf1af1ac
  Akira Hatanaka authored Feb 11, 2013
  bf1af1ac
- [mips] Fix indentation. · 3d38609f
  Akira Hatanaka authored Feb 11, 2013
  3d38609f
- Extend Hexagon hardware loop generation to handle various additional cases: · 9a278f10
  Krzysztof Parzyszek authored Feb 11, 2013
  9a278f10
- Implement HexagonInstrInfo::analyzeCompare. · cfe285e6
  Krzysztof Parzyszek authored Feb 11, 2013
  cfe285e6
- *fixed disassembly of some i386 system insts with intel syntax · d30b1a2a
  Kay Tiong Khoo authored Feb 11, 2013
  d30b1a2a
- R600/SI: Use V_ADD_F32 instead of V_MOV_B32 for clamp/neg/abs modifiers. · 10ed47f9
  Michel Danzer authored Feb 11, 2013
  10ed47f9
- AArch64: fix build on some MSVC versions · be867971
  Tim Northover authored Feb 11, 2013
  be867971
- AArch64: Simplify logic in deciding whether bfi is valid · e2067788
  Tim Northover authored Feb 11, 2013
  e2067788
- Make use of DiagnosticType to provide better AArch64 diagnostics. · 60baeb98
  Tim Northover authored Feb 11, 2013
  60baeb98
- Currently, codegen may spent some time in SDISel passes even if an entire · 615620c9
  Evan Cheng authored Feb 11, 2013
  615620c9