Commits · 7c4a1a8d48c9c52a000d5d9b514cba3f8e1fff7b · Lorenzo Albano / LLVM bpEVL · GitLab

Mar 09, 2016
- libLTO: add a ThinLTOCodeGenerator on the model of LTOCodeGenerator. · 7c4a1a8d
  Mehdi Amini authored Mar 09, 2016
  7c4a1a8d
- FunctionIndex is not optional for renameModuleForThinLTO(), make it a reference (NFC) · bd04e8fe
  Mehdi Amini authored Mar 09, 2016
  bd04e8fe
Mar 08, 2016
- use range-based for loop; NFCI · b8d071bc
  Sanjay Patel authored Mar 08, 2016
  b8d071bc
- fix variable name; NFC · f831fdb5
  Sanjay Patel authored Mar 08, 2016
  f831fdb5
- use range-based loop; NFCI · 5c967236
  Sanjay Patel authored Mar 08, 2016
  5c967236
- Revert r262759 and r262760. · 4340b555
  Quentin Colombet authored Mar 08, 2016
  4340b555
- [AArch64] Add MMOs to unscaled pairs. · e40b9513
  Chad Rosier authored Mar 08, 2016
  e40b9513
- rangify, fix function names; NFCI · eaf06851
  Sanjay Patel authored Mar 08, 2016
  eaf06851
- Invoke DAG postprocessing in the post-RA scheduler · cd99e364
  Krzysztof Parzyszek authored Mar 08, 2016
  cd99e364
- don't repeat function names in documentation comments; NFC · 5b8d7416
  Sanjay Patel authored Mar 08, 2016
  5b8d7416
- [ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) · 5ddea6a8
  Artyom Skrobov authored Mar 08, 2016
  5ddea6a8
- Revert r262599 "[X86][SSE] Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG" · e00b6e72
  Hans Wennborg authored Mar 08, 2016
  e00b6e72
- Add DAG mutation interface to the DFA packetizer · 1a1d78b8
  Krzysztof Parzyszek authored Mar 08, 2016
  1a1d78b8
- AVX512: Add extract_subvector patterns v8i1->v4i1 , v4i1->v2i1. · 999ac754
  Igor Breger authored Mar 08, 2016
  999ac754
- Revert "[InstCombine] Combine A->B->A BitCast" · 974eb0a9
  Junmo Park authored Mar 08, 2016
  974eb0a9
- Fix evaluation order. Spotted by Alexander Riccio! · 3866cc5f
  Peter Collingbourne authored Mar 08, 2016
  3866cc5f
- [Power9] Implement new vsx instructions: load, store instructions for vector and scalar · ba532dc8
  Kit Barton authored Mar 08, 2016
  ba532dc8
- [WebAssembly] Update for spec change from tableswitch to br_table. · 14026064
  Dan Gohman authored Mar 08, 2016
  14026064
- Re-apply "SelectionDAG: Store SDNode operands in an ArrayRecycler" · 671febc0
  Justin Bogner authored Mar 08, 2016
  671febc0
- [MIR] Change the token name for '<' and '>' to be consitent with the LLVM IR parser. · 5e63e78c
  Quentin Colombet authored Mar 08, 2016
  5e63e78c
- [AArch64] Initialize GlobalISel as part of the target initialization. · f574ab29
  Quentin Colombet authored Mar 08, 2016
  f574ab29
- [GlobalISel] Introduce initializer method to support start/stop-after features. · 39293d3a
  Quentin Colombet authored Mar 08, 2016
  39293d3a
- [MIR] Teach the parser/printer that generic virtual registers do not need a register class. · 050b2118
  Quentin Colombet authored Mar 08, 2016
  050b2118
- Revert "SelectionDAG: Store SDNode operands in an ArrayRecycler" · 7e6f09c2
  Justin Bogner authored Mar 08, 2016
  7e6f09c2
- A couple more UB fixes for C++14 sized deallocation. · c2a2830e
  Richard Smith authored Mar 08, 2016
  c2a2830e
- [MIR] Teach the parser how to parse complex types of generic machine instructions. · 287c6bb5
  Quentin Colombet authored Mar 08, 2016
  287c6bb5
- SelectionDAG: Store SDNode operands in an ArrayRecycler · 6543a938
  Justin Bogner authored Mar 08, 2016
  6543a938
- [MIR] Teach the printer how to print complex types for generic machine instructions. · d6554839
  Quentin Colombet authored Mar 08, 2016
  d6554839
- [AsmParser] Expose an API to parse a string starting with a type. · dafed5d7
  Quentin Colombet authored Mar 08, 2016
  dafed5d7
- Revert revisions 262636, 262643, 262679, and 262682. · b1bd398c
  Easwaran Raman authored Mar 08, 2016
  b1bd398c
- [MIR] Print the type of generic machine instructions. · 12350a8e
  Quentin Colombet authored Mar 08, 2016
  12350a8e
- [MIR] Teach the mir parser about types on generic machine instructions. · 85199677
  Quentin Colombet authored Mar 08, 2016
  85199677
- [tsan] Add support for pointer typed atomic stores, loads, and cmpxchg · c1efa64c
  Anna Zaks authored Mar 07, 2016
  c1efa64c
Mar 07, 2016
- [MachineInstr] Get rid of some GlobalISel ifdefs. · 41bea872
  Quentin Colombet authored Mar 07, 2016
  41bea872
- [IR] Provide an API to skip the details of a structured type when printed. · 774b1efa
  Quentin Colombet authored Mar 07, 2016
  774b1efa
- [AsmParser] Add a function to parse a standalone type. · 81e72b4d
  Quentin Colombet authored Mar 07, 2016
  81e72b4d
- [MIR] Teach the MIPrinter about size for generic virtual registers. · 4e14a497
  Quentin Colombet authored Mar 07, 2016
  4e14a497
- AMDGPU: Match more med3 integer patterns · c89f2919
  Matt Arsenault authored Mar 07, 2016
  c89f2919
- [MIR] Teach the parser how to handle the size of generic virtual registers. · 2a831fb8
  Quentin Colombet authored Mar 07, 2016
  2a831fb8
- [MachineRegisterInfo] Add a method to set the size of a virtual register a posteriori. · 1bd7504e
  Quentin Colombet authored Mar 07, 2016
  1bd7504e