Commits · 7e523673981badcd6d91017835b78bba2d89a67b · Lorenzo Albano / LLVM bpEVL · GitLab

Nov 11, 2017
- [X86] Correct the execution domain on ROUND/VROUND instructions. · 0eb4a433
  Craig Topper authored Nov 11, 2017
  0eb4a433
- [X86] Remove the default for one of the arguments to some tablegen multiclasses. NFC · bf9b944e
  Craig Topper authored Nov 11, 2017
  bf9b944e
Nov 10, 2017
- Recommit r317904: [Hexagon] Create HexagonISelDAGToDAG.h, NFC · e8926438
  Krzysztof Parzyszek authored Nov 10, 2017
  e8926438
- AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td · 27b0a033
  Konstantin Zhuravlyov authored Nov 10, 2017
  27b0a033
- Revert "[Hexagon] Create HexagonISelDAGToDAG.h, NFC" · 79dae95f
  Krzysztof Parzyszek authored Nov 10, 2017
  79dae95f
- [X86] Merge the template method selectAddrOfGatherScatterNode into selectVectorAddr. NFCI · bb001c6d
  Craig Topper authored Nov 10, 2017
  bb001c6d
- [RISCV] Silence an unused variable warning in release builds [NFC] · 5f043ae2
  Mandeep Singh Grang authored Nov 10, 2017
  5f043ae2
- [Hexagon] Create HexagonISelDAGToDAG.h, NFC · 89765acc
  Krzysztof Parzyszek authored Nov 10, 2017
  89765acc
- [RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints. · 4b017e68
  Jonas Paulsson authored Nov 10, 2017
  4b017e68
- [X86] Add support for combining FMADDSUB(A, B, FNEG(C))->FMSUBADD(A, B, C) · 1a0da2db
  Craig Topper authored Nov 10, 2017
  1a0da2db
- [AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment · 35845f06
  Yaxun Liu authored Nov 10, 2017
  35845f06
- [AMDGPU] Fix pointer info for pseudo source for r600 · 920cc2f8
  Yaxun Liu authored Nov 10, 2017
  920cc2f8
Nov 09, 2017
- [SystemZ] Add support for the "o" inline asm constraint · d39e9dca
  Ulrich Weigand authored Nov 09, 2017
  d39e9dca
- [mips] Correct microMIP's jump and add unconditional branch pseudo · c2d3e38b
  Simon Dardis authored Nov 09, 2017
  c2d3e38b
- [RISCV] MC layer support for the standard RV32A instruction set extension · 8c345c5a
  Alex Bradbury authored Nov 09, 2017
  8c345c5a
- [RISCV] MC layer support for the standard RV32M instruction set extension · a47514ce
  Alex Bradbury authored Nov 09, 2017
  a47514ce
- Sched model improving on btver2: JFPU01 resource, vtestp* for xmm. · f8c75b87
  Andrew V. Tischenko authored Nov 09, 2017
  f8c75b87
- Add -print-schedule scheduling comments to inline asm. · 3543f0a7
  Andrew V. Tischenko authored Nov 09, 2017
  3543f0a7
- [X86] Give priority to EVEX FMA instructions over FMA4 instructions. · 5bfa5ffe
  Craig Topper authored Nov 09, 2017
  5bfa5ffe
- Fix "default label in switch which covers all enumeration values" warning · bee1964d
  Vitaly Buka authored Nov 09, 2017
  bee1964d
- [X86] Make X86ISD::FMADDS3 isel patterns commutable. · 7a6e294a
  Craig Topper authored Nov 09, 2017
  7a6e294a
- AMDGPU: Merge BUFFER_STORE_DWORD_OFFEN/OFFSET into x2, x4 · 58410f37
  Marek Olsak authored Nov 09, 2017
  58410f37
- AMDGPU: Lower buffer store and atomic intrinsics manually · 5cec6419
  Marek Olsak authored Nov 09, 2017
  5cec6419
- AMDGPU: Merge BUFFER_LOAD_DWORD_OFFSET into x2, x4 · 4c421a2d
  Marek Olsak authored Nov 09, 2017
  4c421a2d
- AMDGPU: Merge BUFFER_LOAD_DWORD_OFFEN into x2, x4 · 6a0548ac
  Marek Olsak authored Nov 09, 2017
  6a0548ac
- AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4 · b953cc36
  Marek Olsak authored Nov 09, 2017
  b953cc36
- AMDGPU: Fold immediate offset into BUFFER_LOAD_DWORD lowered from SMEM · ffadcb74
  Marek Olsak authored Nov 09, 2017
  ffadcb74
- [X86] Make sure we don't read too many operands from X86ISD::FMADDS1/FMADDS3... · 93e27d2e
  Craig Topper authored Nov 09, 2017
  93e27d2e
Nov 08, 2017
- [X86] X86MaskedGatherSDNode shouldn't inherit from MaskedGatherScatterSDNode · cfd51067
  Craig Topper authored Nov 08, 2017
  cfd51067
- [X86] Preserve memory refs when folding loads into divides. · 61f81f96
  Craig Topper authored Nov 08, 2017
  61f81f96
- [X86] Remove an if check on the result of a cast. NFC · 55029d81
  Craig Topper authored Nov 08, 2017
  55029d81
- Revert "Correct dwarf unwind information in function epilogue for X86" · 7adb2fdb
  Reid Kleckner authored Nov 08, 2017
  7adb2fdb
- Set hasSideEffects=0 for PHI and fix affected passes · fa18b9e7
  Alex Bradbury authored Nov 08, 2017
  fa18b9e7
- [X86] Correct the implementation of BEXTR load folding to use the shift as the... · 78a77040
  Craig Topper authored Nov 08, 2017
  78a77040
- [WebAssembly] Update test expectations · 6368442f
  Sam Clegg authored Nov 08, 2017
  6368442f
- [X86] Don't call validateInstruction from MatchAndEmitInstruction when... · e6094f9b
  Craig Topper authored Nov 08, 2017
  e6094f9b
- [WebAssembly] Call signExtend to get sign extended register · 0828ba1e
  Dan Gohman authored Nov 08, 2017
  0828ba1e
- [WebAssembly] Revise the strategy for inline asm. · b465aa05
  Dan Gohman authored Nov 08, 2017
  b465aa05
- [RISCV] Initial support for function calls · a337675c
  Alex Bradbury authored Nov 08, 2017
  a337675c
- [RISCV] Codegen for conditional branches · 74913e1c
  Alex Bradbury authored Nov 08, 2017
  74913e1c