llvm-svn: 85787

llvm-svn: 85767

Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.

PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766

llvm-svn: 85765

Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)

llvm-svn: 85764

llvm-svn: 85746

llvm-svn: 85743

llvm-svn: 85698

them for scalar floating point operations for now.

llvm-svn: 85697

llvm-svn: 85687

llvm-svn: 85685

is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.

llvm-svn: 85675

It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.

llvm-svn: 85643

Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand.  And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.

llvm-svn: 85632

llvm-svn: 85624

llvm-svn: 85610

void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.

llvm-svn: 85590

clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577

llvm-svn: 85546

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517

realignment regardless of whether it's strictly necessary.

llvm-svn: 85476

I'm going to redo this using the OptimizeForSize function attribute.

llvm-svn: 85426

opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411

llvm-svn: 85410

llvm-svn: 85406

llvm-svn: 85381

llvm-svn: 85362

llvm-svn: 85355

use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.

llvm-svn: 85346

llvm-svn: 85335

default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.

llvm-svn: 85333

llvm-svn: 85299

BL_pred and BLr9_pred.

llvm-svn: 85297

instruction format that already takes care of setting this.

llvm-svn: 85280

for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.

llvm-svn: 85271

llvm-svn: 85255

llvm-svn: 85235

llvm-svn: 85186

Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.

llvm-svn: 85184

llvm-svn: 85178