Commits · 921e19563328682eb332124fb7fd01ed74a9da86 · Lorenzo Albano / LLVM bpEVL · GitLab

Aug 16, 2018
- [X86] In EFLAGS copy pass, don't emit EXTRACT_SUBREG instructions since we're after peephole · bde2b43c
  Craig Topper authored Aug 16, 2018
  bde2b43c
- [MI] Change the array of `MachineMemOperand` pointers to be · c73c0307
  Chandler Carruth authored Aug 16, 2018
  c73c0307
- [WebAssembly] Remove temporary workaround for function bitcasts · 3d668d39
  Jacob Gravelle authored Aug 16, 2018
  3d668d39
- [codeview] Use push_macro to avoid conflicts instead of a prefix · bd5d7122
  Reid Kleckner authored Aug 16, 2018
  bd5d7122
- AMDGPU: Custom lower fexp · 7121bed2
  Matt Arsenault authored Aug 16, 2018
  7121bed2
- [MC][X86] Enhance X86 Register expression handling to more closely match GCC. · 7fd992a7
  Nirav Dave authored Aug 16, 2018
  7fd992a7
- Add support for AVX-512 CodeView registers. · 2838b591
  Zachary Turner authored Aug 16, 2018
  2838b591
- [ARM] Ignore GEPs in ARMCodeGenPrepare · 0d511970
  Sam Parker authored Aug 16, 2018
  0d511970
- [ARM] Allow zext in ARMCodeGenPrepare · 0e2f0bd4
  Sam Parker authored Aug 16, 2018
  0e2f0bd4
- [ARM] Allow signed icmps in ARMCodeGenPrepare · 13567dbb
  Sam Parker authored Aug 16, 2018
  13567dbb
- [mips] Remove dead code from MipsPassConfig · a8ac4308
  Simon Atanasyan authored Aug 16, 2018
  a8ac4308
- [X86] Remove masking from the 512-bit padds and psubs intrinsics. Use select in IR instead. · 9c1d9fde
  Craig Topper authored Aug 16, 2018
  9c1d9fde
- [X86] Remove the unused masked 128 and 256-bit masked padds/psubs intrinsics. · 9d6983c9
  Craig Topper authored Aug 16, 2018
  9d6983c9
- [x86] Actually initialize the SLH pass with the x86 backend and use · 00c35c77
  Chandler Carruth authored Aug 16, 2018
  00c35c77
Aug 15, 2018
- AMDGPU: Fold fneg into fmed3 · f533e6b0
  Matt Arsenault authored Aug 15, 2018
  f533e6b0
- AMDGPU: Improve extract_vector_elt reduction combine · a8160737
  Matt Arsenault authored Aug 15, 2018
  a8160737
- AMDGPU: Implement llvm.amdgcn.icmp/fcmp for i16/f16 · b3a80e53
  Matt Arsenault authored Aug 15, 2018
  b3a80e53
- [X86] Improve AVX1 shuffle lowering for v8f32 shuffles where the low half... · 08e08261
  Craig Topper authored Aug 15, 2018
  08e08261
- AMDGPU: Address todo for handling 1/(2 pi) · 6c7ba829
  Matt Arsenault authored Aug 15, 2018
  6c7ba829
- Revert "[ARM] Allow signed icmps in ARMCodeGenPrepare" · ed4239f4
  Vitaly Buka authored Aug 15, 2018
  ed4239f4
- [WebAssembly][NFC] Standardize SIMD multiclass format · 5222cb60
  Thomas Lively authored Aug 15, 2018
  5222cb60
- [WebAssembly] Test commit · 39fe4808
  Thomas Lively authored Aug 15, 2018
  39fe4808
- [WebAssembly] SIMD replace_lane · 82812fb9
  Derek Schuff authored Aug 15, 2018
  82812fb9
- [PowerPC] Enhance the selection(ISD::VSELECT) of vector type · 5b9a4f8e
  Nemanja Ivanovic authored Aug 15, 2018
  5b9a4f8e
- [SystemZ] Replace subreg_r with subreg_h · 2a119b9a
  Krzysztof Parzyszek authored Aug 15, 2018
  2a119b9a
- [SystemZ] New CL option to enable subreg liveness · d5a9c2d5
  Jonas Paulsson authored Aug 15, 2018
  d5a9c2d5
- [ARM] TypeSize lower bound for ARMCodeGenPrepare · fabf7fe5
  Sam Parker authored Aug 15, 2018
  fabf7fe5
- [PowerPC] Don't run BV DAG Combine before legalization if it assumes legal types · 8b4bd09e
  Nemanja Ivanovic authored Aug 15, 2018
  8b4bd09e
- Remove lambda default argument to fix gcc pedantic warning. · f3b5943f
  Simon Pilgrim authored Aug 15, 2018
  f3b5943f
- [ARM] Allow signed icmps in ARMCodeGenPrepare · 6548cd39
  Sam Parker authored Aug 15, 2018
  6548cd39
- [ARM] Allow pointer values in ARMCodeGenPrepare · 7def86bb
  Sam Parker authored Aug 15, 2018
  7def86bb
- [X86] Change legacy SSE scalar fp to integer intrinsics to use specific ISD... · 633fe98e
  Craig Topper authored Aug 15, 2018
  633fe98e
- [SDAG] Update the AVR backend for the SelectionDAG API changes in · 139b3519
  Chandler Carruth authored Aug 15, 2018
  139b3519
- [WebAssembly] SIMD Splats · 4ec8bca1
  Derek Schuff authored Aug 15, 2018
  4ec8bca1
- [SDAG] Remove the reliance on MI's allocation strategy for · 66654b72
  Chandler Carruth authored Aug 14, 2018
  66654b72
- [ARM] Make PerformSHLSimplify add nodes to the DAG worklist correctly. · 0d12e90b
  Eli Friedman authored Aug 14, 2018
  0d12e90b
Aug 14, 2018
- [WebAssembly] Fix encoding of non-SIMD vector-typed instructions · c9c711a0
  Heejin Ahn authored Aug 14, 2018
  c9c711a0
- [WebAssembly] SIMD extract_lane · a0fd9c3e
  Heejin Ahn authored Aug 14, 2018
  a0fd9c3e
- [Tablegen][MCInstPredicate] Removed redundant template argument from class... · 9eaf5aa0
  Andrea Di Biagio authored Aug 14, 2018
  9eaf5aa0
- [X86][SSE] Avoid duplicate shuffle input sources in combineX86ShufflesRecursively · 2ce3d6e1
  Simon Pilgrim authored Aug 14, 2018
  2ce3d6e1