llvm-svn: 320397

llvm-svn: 320395

llvm-svn: 320392

Tag LWP instructions as WriteSystem

llvm-svn: 320387

llvm-svn: 320386

llvm-svn: 320385

llvm-svn: 320384

llvm-svn: 320383

llvm-svn: 320382

llvm-svn: 320380

llvm-svn: 320379

llvm-svn: 320376

  
At first, I tried to thread the x86 needle and use a target hook (isVectorShiftByScalarCheap())
to disable the transform only for non-splat pow-of-2 constants, but not AVX2, but only some
element types, but...it's difficult.

Here we just avoid the loop with the x86 vector transform that conflicts with the general DAG
combine and preserve all of the existing behavior AFAICT otherwise.

Some tests that will probably fail if someone does try to restrict this in a more targeted way
for x86-only may be found in:

test/CodeGen/X86/combine-mul.ll
test/CodeGen/X86/vector-mul.ll
test/CodeGen/X86/widen_arith-5.ll

This should prevent the infinite looping seen with:
https://bugs.llvm.org/show_bug.cgi?id=35579

Differential Revision: https://reviews.llvm.org/D41040

llvm-svn: 320374

llvm-svn: 320371

llvm-svn: 320370

llvm-svn: 320361

llvm-svn: 320356

We should probably also fold (mulhs/u X, 1) for vectors, but that's harder.

llvm-svn: 320344

llvm-svn: 320342

[X86] Add a test case for masked scatter where the index needs to be legalized from v2i32 while other types are legal.

llvm-svn: 320340

llvm-svn: 320334

llvm-svn: 320333

Include i686 (non-REX) variant tests as well

llvm-svn: 320332

llvm-svn: 320331

llvm-svn: 320330

llvm-svn: 320329

llvm-svn: 320328

This matches AVX512 version and is more consistent overall. And improves our scheduler models.

In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses.

llvm-svn: 320325

llvm-svn: 320322

Split off some 'n' instruction versions to make it clearer when WAIT is being inserted

llvm-svn: 320321

[X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper suffix. Fix the scheduling information for some of them.

Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)'

llvm-svn: 320320

llvm-svn: 320319

Locally tag COPY as WriteMove, which has caused some reg-reg + reg-mem instruction tests to reorder.

llvm-svn: 320308

llvm-svn: 320307

llvm-svn: 320305

Based on the fact that the 'Y' version of the instruction is next to this, I assume Z256 is the intended value.

llvm-svn: 320295

The VEX versions were present but not the legacy SSE versions.

llvm-svn: 320294

[X86] Correct the _Int part of more scheduler model instrexes. Put _b in the correct order relative to _Int

llvm-svn: 320282

llvm-svn: 320280

[X86] Fix bad regular expressions in the scheduler models. Question marks should be outside of multicharacter parenthesized expressions

If the question mark is inside the parentheses it only applies to the single character proceeding it.

I had to make a few additional cleanups to fix some duplicate warnings that were exposed by fixing this.

llvm-svn: 320279