Summary:
Only run completion when we were trigerred on '->' and '::', otherwise
send an error code in return.
To avoid automatically invoking completions in cases like 'a >^' or
'a ? b :^'.

Reviewers: hokein

Reviewed By: hokein

Subscribers: ioeric, MaskRay, jkorous, arphaman, kadircet, cfe-commits

Differential Revision: https://reviews.llvm.org/D55994

llvm-svn: 350304

llvm-svn: 350303

This file was missing on the patch

llvm-svn: 350302

Use X86/X64 check prefixes
Use nounwind to reduce cfi noise

llvm-svn: 350301

Enables SLP vectorization for the SSE2 PADDS/PADDUS/PSUBS/PSUBUS style intrinsics

llvm-svn: 350300

SB (Speculative Barrier) is only mandatory from 8.5
onwards but is optional from Armv8.0-A. This patch adds a command
line option to enable SB, as it was previously only possible to
enable by selecting -march=armv8.5-a.

This patch also renames FeatureSpecRestrict to FeatureSB.

Reviewed By: olista01, LukeCheeseman

Differential Revision: https://reviews.llvm.org/D55990

llvm-svn: 350299

llvm-svn: 350298

llvm-svn: 350297

llvm-svn: 350296

Costs for real SSE2 instructions

llvm-svn: 350295

llvm-svn: 350294

llvm-svn: 350293

Summary:
The commit rL348922 introduced a means to set Metadata
section kind for a global variable, if its explicit section
name was prefixed with ".AMDGPU.metadata.".

This patch changes that prefix to ".AMDGPU.comment.",
as "metadata" in the section name might lead to
ambiguity with metadata used by AMD PAL runtime.

Change-Id: Idd4748800d6fe801441d91595fc21e5a4171e668

Reviewers: kzhuravl

Reviewed By: kzhuravl

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D56197

llvm-svn: 350292

Summary:
instead of returning the architecture through by-ref argument and a
boolean value indicating success, we can just return the ArchSpec
directly. Since the ArchSpec already has an invalid state, it can be
used to denote the failure without the additional bool.

Reviewers: clayborg, zturner, espindola

Subscribers: emaste, arichardson, JDevlieghere, lldb-commits

Differential Revision: https://reviews.llvm.org/D56129

llvm-svn: 350291

The commit caused unclear failures in http://green.lab.llvm.org/green//job/lldb-cmake/
will revert if the error reappears

Differential Revision: https://reviews.llvm.org/D56084

llvm-svn: 350290

A DBG_VALUE between a two-address instruction and a following COPY
would prevent rescheduleMIBelowKill optimization inside
TwoAddressInstructionPass.

Differential Revision: https://reviews.llvm.org/D55987

llvm-svn: 350289

There can be multiple local symbols with the same name (for e.g.
comdat sections), and thus the symbol name itself isn't enough
to disambiguate symbols.

Differential Revision: https://reviews.llvm.org/D56140

llvm-svn: 350288

[X86] Add test cases for opportunities to use KTEST when check if the result of ANDing two mask registers is zero.

The test cases are constructed to avoid folding the AND into a masked compare operation.

Currently we emit a KAND and a KORTEST for these cases.

llvm-svn: 350287

Fixing up style issues around the area to prepare for
a larger differential.

llvm-svn: 350286

When switched to the MI scheduler for P9, the hardware is modeled as out of order.
However, inside the MI Scheduler algorithm, we still use the in-order scheduling model
as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer
the op. So, only when all the available instructions issued, the pending instruction
could be scheduled. That is not true for our P9 hw in fact.

This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is
picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017.

With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows:

x264_r: +6.95%
cactuBSSN_r: +6.94%
lbm_r: +4.11%
xz_r: -3.85%

And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. 

Reviewer: Nemanjai
Differential Revision: https://reviews.llvm.org/D55810

llvm-svn: 350285

OptimizeAutoreleaseRVCall skips optimizing llvm.objc.autoreleaseReturnValue if it
sees a user which is llvm.objc.retainAutoreleasedReturnValue, and if they have
equivalent arguments (either identical or equivalent PHIs). It then assumes that
ObjCARCOpt::OptimizeRetainRVCall will optimize the pair instead.

Trouble is, ObjCARCOpt::OptimizeRetainRVCall doesn't know about equivalent PHIs
so optimizes in a different way and we are left with an unoptimized llvm.objc.autoreleaseReturnValue.

This teaches ObjCARCOpt::OptimizeRetainRVCall to also understand PHI equivalence.

rdar://problem/47005143

Reviewed By: ahatanak

Differential Revision: https://reviews.llvm.org/D56235

llvm-svn: 350284

After the test was reformatted using clang-format the numbers became invalid.

llvm-svn: 350283

This change ensures that the libclang CXCursor represents the CoroutineBody
and the Coreturn statement using the appropriate CXCursor_UnexposedStmt kind
instead of CXCursor_UnexposedExpr. The problem with CXCursor_UnexposedExpr is
that the consumer functions assumed that CoroutineBody/Coreturn statements
were valid expressions and performed an invalid downcast to Expr causing
assertion failures or other crashes.

rdar://40204290

llvm-svn: 350282

llvm-svn: 350281

Calculate which item is being held and then display it with the appropriate type. We also 
optimize the display of PointerUnion3 to take advantage of our knowing that the IntMask is
always 1 in PointerUnion types

llvm-svn: 350280

Summary: Add read[only|write] PIC relocation models to the C API and teach the TargetMachine API about it.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D56187

llvm-svn: 350279

For some reason, the cmake build on my macbook has
LLVM_HOST_TRIPLE:STRING=i386-apple-darwin16.7.0 .
test/Driver/darwin-sdk-version.c assumed that the host triple is 64-bit, so
make it resilient against 32-bit host triples.

Differential Revision: https://reviews.llvm.org/D56067

llvm-svn: 350278

And add a test for it.

llvm-svn: 350277

Summary:
Sometimes it's useful to emit assembly after LTO stage to modify it manually. Emitting precodegen bitcode file (via save-temps plugin option) and then feeding it to llc doesn't always give the same binary as original.
This patch is simpler alternative to https://reviews.llvm.org/D24020.

Patch by Denis Bakhvalov.

Reviewers: mehdi_amini, tejohnson

Reviewed By: tejohnson

Subscribers: MaskRay, inglorion, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D56114

llvm-svn: 350276

llvm-svn: 350275

This is an alternate patch for the bug reported in
https://bugs.llvm.org/show_bug.cgi?id=39816 ("lldb doesn't show a file
of line entry for big project"). This limits the number of lines in a
source file to 32M, which I think is reasonable even for preprocessed
source inputs.

Differential Revision: https://reviews.llvm.org/D56218

llvm-svn: 350274

llvm-svn: 350273

The peephole pass isn't always able to fold the load because it can't commute the implicit usage of AL/AX/EAX/RAX.

llvm-svn: 350272

[X86] Add test cases to show that we fail to fold loads into i8 smulo and i8/i16/i32/i64 umulo lowering without the assistance of the peephole pass. NFC

llvm-svn: 350271

Summary:
This was previously ignored and an incorrect value generated.

Also fixed Disassembler's handling of block_type.

Reviewers: dschuff, aheejin

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D56092

llvm-svn: 350270

Summary:
Alias can make one (but not all) live, we still need to scan all others if this symbol is reachable
from somewhere else.

Reviewers: tejohnson, grimar

Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D56117

llvm-svn: 350269

Removes some unneeded includes from the driver.

llvm-svn: 350267

llvm-svn: 350266

shl by 32 is undefined. This was intended to be a shl by 31 as part
of a rotate sequence.

llvm-svn: 350265

llvm-svn: 350264