using pred_begin/end.  It is much faster.

llvm-svn: 96079

instead of with pred_begin/end.

llvm-svn: 96078

llvm-svn: 96076

llvm-svn: 96075

tables.

llvm-svn: 96073

When coalescing with a physreg, remember to add imp-def and imp-kill when
dealing with sub-registers.

Also fix a related bug in VirtRegRewriter where substitutePhysReg may
reallocate the operand list on an instruction and invalidate the reg_iterator.
This can happen when a register is mentioned twice on the same instruction.

llvm-svn: 96072

deterministically sorted.

llvm-svn: 96071

created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.

llvm-svn: 96069

Functions explicitly marked inline will get an inlining threshold slightly
more aggressive than the default for -O3. This means than -O3 builds are
mostly unaffected while -Os builds will be a bit bigger and faster.

The difference depends entirely on how many 'inline's are sprinkled on the
source.

In the CINT2006 suite, only these tests are significantly affected under -Os:

               Size   Time
471.omnetpp   +1.63% -1.85%
473.astar     +4.01% -6.02%
483.xalancbmk +4.60%  0.00%

Note that 483.xalancbmk runs too quickly to give useful timing results.

llvm-svn: 96066

llvm-svn: 96065

MC/AsmParser: Attempt to constant fold expressions up-front. This ensures we avoid fixups for obvious cases like '-(16)'.

llvm-svn: 96064

llvm-svn: 96063

We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.

llvm-svn: 96059

fix swapgs to be spelled right.

llvm-svn: 96058

phi cycles.  Adjust a few tests to keep dead instructions from being optimized
away.  This (together with my previous change for phi cycles) fixes Apple
radar 7627077.

llvm-svn: 96057

SCEVAddRecExpr doesn't necessarily dominate blocks merely dominated
by all of its operands. This fixes an abort compiling 403.gcc.

llvm-svn: 96056

llvm-svn: 96055

separate LLVMContexts.

llvm-svn: 96051

encoder and decoder by using new MRM_ forms.

llvm-svn: 96048

llvm-svn: 96045

whose opcodes extend into the ModR/M field using the
Form field of the instruction rather than by special
casing each instruction.  Commented out the special
casing of VMCALL, which is the first instruction to use
this special form.  While I was in the neighborhood,
added a few comments for people modifying the Intel
disassembler. 

llvm-svn: 96043

rip-relative addresses, and add a testcase.

llvm-svn: 96040

The solution there produces correct code, but is seriously
deficient in several ways.

llvm-svn: 96039

llvm-svn: 96038

Patch by Shivram K!

llvm-svn: 96037

addressing.  This isn't complete because I need an MCContext
to generate new MCExprs.

llvm-svn: 96036

Plus add two formats: MiscFrm and ThumbMiscFrm.  Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.

llvm-svn: 96032

llvm-svn: 96031

llvm-svn: 96029

llvm-svn: 96028

llvm-svn: 96027

is pc relative or not, mark call and branches as pcrel.

llvm-svn: 96026

Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case.

llvm-svn: 96023

llvm-svn: 96020

llvm-svn: 96019

llvm-svn: 96018

stack frame, the prolog/epilog code was using the same
register for the copy of CR and the address of the save slot.  Oops.
This is fixed here for Darwin, sort of, by reserving R2 for this case.
A better way would be to do the store before the decrement of SP,
which is safe on Darwin due to the red zone.

SVR4 probably has the same problem, but I don't know how to fix it;
there is no red zone and R2 is already used for something else.
I'm going to leave it to someone interested in that target.

Better still would be to rewrite the CR-saving code completely;
spilling each CR subregister individually is horrible code.

llvm-svn: 96015

llvm-svn: 96011

llvm-svn: 96010

llvm-svn: 96008