llvm-svn: 55777

Dan or Evan, please review.

llvm-svn: 55764

llvm-svn: 55763

Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support!

llvm-svn: 55756

llvm-svn: 55715

llvm-svn: 55702

doesNotAccessMemory, check doesNotAccessMemory
first, since otherwise functions may be
marked readonly rather than readnone.

llvm-svn: 55697

callgraph, when one member of a SCC calls another
then the analysis would drop to mod-ref because
there is (usually) no function info for the callee
yet; fix this.  Teach the analysis about function
attributes, in particular the readonly attribute
(which requires being careful about globals).

llvm-svn: 55696

llvm-svn: 55695

llvm-svn: 55693

be folded. Instead, fail to fold the entire vector.

We could also return a vector with some elements folded and some not. If anyone
thinks that's a better approach, please speak up!

llvm-svn: 55689

llvm-svn: 55680

llvm-svn: 55674

llvm-svn: 55673

llvm-svn: 55657

xfail old test for ppc.

llvm-svn: 55651

llvm-svn: 55648

llvm-svn: 55605

instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.

llvm-svn: 55582

combiner can now generate ROTR if the backend says that it can handle it. Cell
SPU says this, but gets an error from code gen saying that it can't select
ROTR. I'm xfailing this test until this can be fixed.

llvm-svn: 55579

Based on patch by Giorgos Korfiatis.

llvm-svn: 55570

Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction.

llvm-svn: 55564

Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).

llvm-svn: 55558

llvm-svn: 55556

llvm-svn: 55553

llvm-svn: 55550

llvm-svn: 55540

nameless values, such as:

%3 = add i32 4, 2

This fixes the first half of PR2480

llvm-svn: 55539

llvm-svn: 55521

In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN

llvm-svn: 55499

its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.

This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.

llvm-svn: 55498

Benchmarks/sim/sim, and others on x86-64.

llvm-svn: 55475

If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy.

llvm-svn: 55467

Feel free to fix a better way!

llvm-svn: 55456

verifier. See PR2711 for details.

llvm-svn: 55414

llvm-svn: 55401

llvm-svn: 55374

assign it to a version of the xmm register with the regclass that matches its
type.  This fixes PR2715, a bug handling some crazy xpcom case in mozilla.

llvm-svn: 55358

Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.

llvm-svn: 55338

bitcast of constants in fast isel.

llvm-svn: 55325