llvm-svn: 319029

Differential Revision: https://reviews.llvm.org/D40124

llvm-svn: 318977

Reduces spsce used and makes it easier to compare the 2 values for the equivalent instructions

llvm-svn: 318541

llvm-svn: 318402

Some CPUs are already overriding these sign extension instructions but we should be able to use the WriteALU schedule class by default.

Differential Revision: https://reviews.llvm.org/D39899

llvm-svn: 318308

 - CBW etc sign extensions
 - CLC/CLD/CMC flag modifiers
 - CPUID

llvm-svn: 317885

Not sure if we want to add the more exotic system instructions (IRET etc.) as well?

llvm-svn: 317882

Differential Revision: https://reviews.llvm.org/D39728

llvm-svn: 317782

These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir.

Currently waiting for D39728 to land to add support for scheduler comments for inline asm.

llvm-svn: 317698