Commits · c2066d19cda20d0e98b95da1493e6c3f26fd9618 · Lorenzo Albano / LLVM bpEVL · GitLab

Aug 03, 2022
- [X86][MC] Always emit `rep` prefix for `bsf` · c2066d19
  Phoebe Wang authored Aug 03, 2022
  c2066d19
- Fix a stack overflow in ScalarEvolution. · 7ae5d00a
  Johannes Reifferscheid authored Aug 03, 2022
  7ae5d00a
- ManagedStatic: remove from PluginLoader · 2fe3589a
  Nicolai Hähnle authored Jun 29, 2022
  2fe3589a
- ManagedStatic: remove from TimeProfiler · 48c401a6
  Nicolai Hähnle authored Jun 29, 2022
  48c401a6
- [X86] Using `X86MemOperand` instead of `Operand` for `i32mem_TC` and `i64mem_TC` · 5bbb0a83
  Liu, Chen3 authored Aug 03, 2022
  5bbb0a83
- [AA] Make ModRefInfo a bitmask enum (NFC) · b128e057
  Nikita Popov authored Aug 01, 2022
  b128e057
- [SCEV] Use context to strengthen flags of BinOps · 34ae308c
  Max Kazantsev authored Aug 03, 2022
  34ae308c
- [RISCV] Use InstVisitor in RISCVCodeGenPrepare. NFC · f19497f7
  Craig Topper authored Aug 02, 2022
  f19497f7
- [IRBuilder] Handle constexpr-bitcast for IRBuilder::CreateThreadLocalAddress · ce1b24cc
  Chuanqi Xu authored Aug 03, 2022
  ce1b24cc
- [llvm][NFC] Refactor code to use ProfDataUtils · d434e40f
  Paul Kirth authored Jul 27, 2022
  d434e40f
- [AMDGPU] Add CL option for max-ilp scheduler. · 3dfa5626
  Austin Kerbow authored Aug 02, 2022
  3dfa5626
- [RISCV] Fix operand number in debug message in RISCVMergeBaseOffset. · a5605f1f
  Craig Topper authored Aug 02, 2022
  a5605f1f
Aug 02, 2022
- CommandLine: add and use cl::SubCommand::get{All,TopLevel} · f7872cdc
  Nicolai Hähnle authored Jun 29, 2022
  f7872cdc
- [AMDGPU] Add llvm_unreachable to switch statement added in d7100b39 . · 40eec276
  Austin Kerbow authored Aug 02, 2022
  
  40eec276
- [nfc] Remove unused parameter in TailDuplicator::duplicateSimpleBB · 4146c175
  Mircea Trofin authored Aug 02, 2022
  4146c175
- [AMDGPU] Add GCNMaxILPSchedStrategy · d7100b39
  Austin Kerbow authored Jul 30, 2022
  d7100b39
- [NFC][DirectX backend] Fix crash when emit_obj for DirectX backend. · 20f7f9b7
  Xiang Li authored Jul 31, 2022
  20f7f9b7
- [StandardInstrumentations] Assign names to basic blocks without names · 43aa4ac7
  Arthur Eubanks authored Jul 26, 2022
  43aa4ac7
- [GIsel] Add missing libcall for G_MUL to LegalizerHelper · b3837537
  Kai Nacke authored Aug 02, 2022
  b3837537
- [AArch64] Treat x18 as callee-saved in functions with Windows calling convention on Darwin · 71aecbb7
  Vladislav Dzhidzhoev authored Jul 27, 2022
  71aecbb7
- [DebugInfo] Test commit: update irrelevant comments · f6d9f000
  Vladislav Dzhidzhoev authored Aug 02, 2022
  f6d9f000
- [MIPS] Expose the ZERO register as a constant physical register · 85a6dd50
  Guozhi Wei authored Aug 02, 2022
  85a6dd50
- [RISCV] Add scheduler classes to PseudoVMV*R_V. · ae687783
  Craig Topper authored Aug 02, 2022
  ae687783
- [RISCV] Add scheduler class to PseudoReadVLENB. · 2e5c516a
  Craig Topper authored Aug 02, 2022
  2e5c516a
- [AMDGPU] avoid blind converting to VALU REG_SEQUENCE and PHIs · a321d95b
  Alexander Timofeev authored Aug 01, 2022
  a321d95b
- [AMDGPU] Remove IR SpeculativeExecution pass from codegen pipeline · e301e071
  Jay Foad authored Jul 21, 2022
  e301e071
- [AMDGPU] Take advantage of VOP3 literals in convertToThreeAddress · c24d68ff
  Jay Foad authored Aug 02, 2022
  c24d68ff
- [LV] Recognize store of invariant value to invariant address as uniform · 0b47615f
  Philip Reames authored Aug 02, 2022
  0b47615f
- [X86][FP16] Fix vector_shuffle and lowering without f16c feature problems · 23021d4d
  Phoebe Wang authored Aug 02, 2022
  23021d4d
- [IRBuilder] CreateIntrinsic with implicit mangling · bb283241
  Jay Foad authored Jul 29, 2022
  bb283241
- [AArch64] Fold Mul(And(Srl(X, 15), 0x10001), 0xffff) to CMLTz · 1206f72e
  David Green authored Aug 02, 2022
  1206f72e
- [DAG] matchRotateSub - ensure the (pre-extended) shift amount is wide enough... · b651fdff
  Simon Pilgrim authored Aug 02, 2022
  b651fdff
- [AArch64][LoopVectorize] Disable tail-folding for SVE when loop has interleaved accesses · 4ef9cb6c
  David Sherwood authored Jul 18, 2022
  4ef9cb6c
- [RISCV][NFCI] Set TransientStackAlignment and rely on it rather than... · 5ad59c9e
  Alex Bradbury authored Aug 02, 2022
  5ad59c9e
- Outliner: add "target-cpu" feature from source function to outlined · b586dc21
  Tim Northover authored Jul 29, 2022
  b586dc21
- [RISCV][NFC] Use defined variable instead some code. · e208bab5
  wanglian authored Aug 02, 2022
  e208bab5
- [LV] Refactor getExtendedAddReductionCost to support other extended reduction more than Add. · e38af7ba
  jacquesguan authored Aug 01, 2022
  e38af7ba
- [SelectOpti] Auto-disable other cmov optis when the new select-opti pass is enabled · 995b61cd
  Sotiris Apostolakis authored Aug 01, 2022
  995b61cd
- [IntelJITEvents] Add missing include. · 5680ef87
  Sunho Kim authored Aug 02, 2022
  5680ef87
- [InstCombine] Correct strtol folding with nonnull endptr · bcef4d23
  Martin Sebor authored Aug 01, 2022
  bcef4d23