Commits · d8b85584f23b78788d4bf8cabe84224baa7029e6 · Lorenzo Albano / LLVM bpEVL · GitLab

Jan 27, 2017
- [Hexagon] Remove unused variable (and silence a warning) · 35ce5dac
  Krzysztof Parzyszek authored Jan 27, 2017
  35ce5dac
- AMDGPU/SI: Move some ISel helpers into utils so they can be shared with GISel · 08efb7eb
  Tom Stellard authored Jan 27, 2017
  08efb7eb
- [AMDGPU] Grab MCSubtargetInfo from TargetMachine instead of constructing it · a304c836
  Konstantin Zhuravlyov authored Jan 27, 2017
  a304c836
- [X86] Adding FFREEP instruction. · 535e7d15
  Chris Ray authored Jan 27, 2017
  535e7d15
- AMDGPU: Enable FeatureFlatForGlobal on Volcanic Islands · d8f7ea38
  Matt Arsenault authored Jan 27, 2017
  d8f7ea38
- NVPTX: Make NVPTXInferAddressSpaces preserve CFG · 32b9600a
  Matt Arsenault authored Jan 27, 2017
  32b9600a
- [AMDGPU] Turn AMDGPUUnifyMetadata back into module pass · f6c1feb8
  Stanislav Mekhanoshin authored Jan 27, 2017
  f6c1feb8
- [mips] Recommit: "N64 static relocation model support" · ca74dd79
  Simon Dardis authored Jan 27, 2017
  ca74dd79
- ARM: fix vectorized division on WoA · 26c00e37
  Saleem Abdulrasool authored Jan 27, 2017
  26c00e37
- NVPTXCodeGen: Add IPO to libdeps, since r293189. · 0d299191
  NAKAMURA Takumi authored Jan 27, 2017
  0d299191
- [ARM][LegalizerInfo] Specify the type of the opcode. · 89dbea06
  Quentin Colombet authored Jan 27, 2017
  89dbea06
- [AArch64][LegalizerInfo] Specify the type of the opcode. · 24203cf9
  Quentin Colombet authored Jan 27, 2017
  24203cf9
- Revert "[AArch64][LegalizerInfo] Specify the type of the initialization list." · e15e460c
  Quentin Colombet authored Jan 27, 2017
  e15e460c
- [AArch64][LegalizerInfo] Specify the type of the initialization list. · 86fc8305
  Quentin Colombet authored Jan 27, 2017
  86fc8305
- [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). · e6cf4374
  Eugene Zelenko authored Jan 26, 2017
  e6cf4374
- [Hexagon] Require IPO library in Hexagon build · d6c8e3c9
  Krzysztof Parzyszek authored Jan 26, 2017
  d6c8e3c9
Jan 26, 2017
- [Hexagon] Add Hexagon-specific loop idiom recognition pass · c8b94386
  Krzysztof Parzyszek authored Jan 26, 2017
  c8b94386
- [AArch64] Refine Kryo Machine Model · b73d2962
  Balaram Makam authored Jan 26, 2017
  b73d2962
- [PPC] cleanup of mayLoad/mayStore flags and memory operands. · 3c8c385a
  Sean Fertile authored Jan 26, 2017
  3c8c385a
- Replace addEarlyAsPossiblePasses callback with adjustPassManager · 81598117
  Stanislav Mekhanoshin authored Jan 26, 2017
  81598117
- Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled." · d32a421f
  Nirav Dave authored Jan 26, 2017
  d32a421f
- [XRay][Arm32] Reduce the portion of the stub and implement more staging for tail calls - in LLVM · e09ba748
  Serge Rogatch authored Jan 26, 2017
  e09ba748
- In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. · de6516c4
  Nirav Dave authored Jan 26, 2017
  de6516c4
- Use shouldAssumeDSOLocal in classifyGlobalReference. · 82149a1a
  Rafael Espindola authored Jan 26, 2017
  82149a1a
- [X86][SSE] Add support for combining ANDNP byte masks with target shuffles · 027bb453
  Simon Pilgrim authored Jan 26, 2017
  027bb453
- [X86][SSE] Pull out target shuffle resolve code into helper. NFCI. · 3057fd53
  Simon Pilgrim authored Jan 26, 2017
  3057fd53
- [AMDGPU] Fix typo in GCNSchedStrategy · 75d1de90
  Valery Pykhtin authored Jan 26, 2017
  75d1de90
- Revert "[mips] N64 static relocation model support" · 5b67a4f7
  Simon Dardis authored Jan 26, 2017
  5b67a4f7
- [mips] N64 static relocation model support · 09e65efd
  Simon Dardis authored Jan 26, 2017
  09e65efd
- [ARM] GlobalISel: Load i1, i8 and i16 args from stack · 278c722e
  Diana Picus authored Jan 26, 2017
  278c722e
- [AVX-512] Move the combine that runs combineBitcastForMaskedOp to the last DAG... · bad53cce
  Craig Topper authored Jan 26, 2017
  bad53cce
- [X86] When bitcasting INSERT_SUBVECTOR/EXTRACT_SUBVECTOR to match masked... · f0bab7b7
  Craig Topper authored Jan 26, 2017
  f0bab7b7
- [TargetTransformInfo] Refactor and improve getScalarizationOverhead() · 8e2f948e
  Jonas Paulsson authored Jan 26, 2017
  8e2f948e
- AMDGPU: Fold fneg into round instructions · 53f0cc23
  Matt Arsenault authored Jan 26, 2017
  53f0cc23
Jan 25, 2017
- Revert "[PPC] Give unaligned memory access lower cost on processor that supports it" · 65144c85
  Daniel Jasper authored Jan 25, 2017
  65144c85
- [AMDGPU] Bump up n_type for metadata v2 · 400771ed
  Konstantin Zhuravlyov authored Jan 25, 2017
  400771ed
- AMDGPU: Set call_convention bit in kernel_code_t · 5d910194
  Matt Arsenault authored Jan 25, 2017
  5d910194
- [XRay][AArch64] More staging for tail call support in XRay on AArch64 - in LLVM · bc2d3439
  Serge Rogatch authored Jan 25, 2017
  bc2d3439
- Add iterator_range<regclass_iterator> to {Target,MC}RegisterInfo, NFC · ee9aa3ff
  Krzysztof Parzyszek authored Jan 25, 2017
  ee9aa3ff
- PowerPC: Slight cleanup of getReservedRegs(); NFC · aeb8e339
  Matthias Braun authored Jan 25, 2017
  aeb8e339