llvm-svn: 86453

Also, fix a few other details of the cmake test target and rename it to
'check'. CMake tests now work for the most part, but there are a handful of
failures left due to missing site.exp bits.

llvm-svn: 86452

and generate it for CMake builds as well.

llvm-svn: 86451

llvm-svn: 86450

llvm-svn: 86445

llvm-svn: 86444

not turn a PHI in a legal type into a PHI of an illegal type, and
add a new optimization that breaks up insane integer PHI nodes into
small pieces (PR3451).

llvm-svn: 86443

llvm-svn: 86434

llvm-svn: 86429

llvm-svn: 86428

llvm-svn: 86418

1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect.  The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.

llvm-svn: 86415

llvm-svn: 86403

Eric, please investigate.

llvm-svn: 86399

(eliminating some extends) if the new type of the
computation is legal or if both the source and dest
are illegal.  This prevents instcombine from changing big
chains of computation into i64 on 32-bit targets for 
example.

llvm-svn: 86398

llvm-svn: 86392

llvm-gcc-i386-darwin9 build bot.

llvm-svn: 86391

llvm-svn: 86385

llvm-svn: 86384

llvm-svn: 86382

Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.

llvm-svn: 86375

of movhps as the constraint.  Changes optimizations so
update testcases as appropriate as well.

llvm-svn: 86360

a store.

llvm-svn: 86359

(making pred factoring only happen if threading is guaranteed
to be successful).

This now survives an X86-64 bootstrap of llvm-gcc.

llvm-svn: 86355

llvm-svn: 86354

things. Back out part of r86349 for a moment.

llvm-svn: 86353

and add a .ll to demo the new capability.

llvm-svn: 86349

llvm-svn: 86345

llvm-svn: 86330

  except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.

llvm-svn: 86328

86289, 86278, 86270, 86267, 86266 & 86264
Chris, please take a look.

llvm-svn: 86321

Here is the original commit message:

This commit updates malloc optimizations to operate on malloc calls that have constant int size arguments.

Update CreateMalloc so that its callers specify the size to allocate:
MallocInst-autoupgrade users use non-TargetData-computed allocation sizes.
Optimization uses use TargetData to compute the allocation size.

Now that malloc calls can have constant sizes, update isArrayMallocHelper() to use TargetData to determine the size of the malloced type and the size of malloced arrays.
Extend getMallocType() to support malloc calls that have non-bitcast uses.

Update OptimizeGlobalAddressOfMalloc() to optimize malloc calls that have non-bitcast uses.  The bitcast use of a malloc call has to be treated specially here because the uses of the bitcast need to be replaced and the bitcast needs to be erased (just like the malloc call) for OptimizeGlobalAddressOfMalloc() to work correctly.

Update PerformHeapAllocSRoA() to optimize malloc calls that have non-bitcast uses.  The bitcast use of the malloc is not handled specially here because ReplaceUsesOfMallocWithGlobal replaces through the bitcast use.

Update OptimizeOnceStoredGlobal() to not care about the malloc calls' bitcast use.

Update all globalopt malloc tests to not rely on autoupgraded-MallocInsts, but instead use explicit malloc calls with correct allocation sizes.

llvm-svn: 86311

  load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304

llvm-svn: 86303

will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.

llvm-svn: 86301

llvm-svn: 86298

Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead.

llvm-svn: 86294

llvm-svn: 86281

llvm-svn: 86278

llvm-svn: 86269