Commits · f41e3f56a5b337ac78816c7555add946eed725ca · Lorenzo Albano / LLVM bpEVL · GitLab

May 20, 2013
- VSTn instructions have a number of encoding constraints which are not... · f41e3f56
  Mihai Popa authored May 20, 2013
  f41e3f56
- Q registers are encoded in fields of the same length as D registers. As Q... · dcf09227
  Mihai Popa authored May 20, 2013
  dcf09227
- [SystemZ] Add long branch pass · 312425f3
  Richard Sandiford authored May 20, 2013
  312425f3
- [NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs · 01f89f04
  Justin Holewinski authored May 20, 2013
  01f89f04
- [NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need... · 700b6fa9
  Justin Holewinski authored May 20, 2013
  700b6fa9
- PR15868 fix. · d0e34a20
  Stepan Dyatkovskiy authored May 20, 2013
  d0e34a20
- Also expand 64-bit bitcasts. · f9278003
  Jakob Stoklund Olesen authored May 20, 2013
  f9278003
- Implement spill and fill of I64Regs. · c7bc5fbc
  Jakob Stoklund Olesen authored May 20, 2013
  c7bc5fbc
- Mark i64 SETCC as expand so it is turned into a SELECT_CC. · 751e9b84
  Jakob Stoklund Olesen authored May 20, 2013
  751e9b84
- Replace some bit operations with simpler ones. No functionality change. · 8bad66e5
  Benjamin Kramer authored May 19, 2013
  8bad66e5
May 19, 2013
- Don't use %g0 to materialize 0 directly. · 86c5469d
  Jakob Stoklund Olesen authored May 19, 2013
  86c5469d
- Select i64 values with %icc conditions. · 92ebf115
  Jakob Stoklund Olesen authored May 19, 2013
  92ebf115
- Add floating point selects on %xcc predicates. · 7ca944b9
  Jakob Stoklund Olesen authored May 19, 2013
  7ca944b9
- Implement SPselectfcc for i64 operands. · 4a78c86a
  Jakob Stoklund Olesen authored May 19, 2013
  4a78c86a
- [Sparc] Rearrange integer registers' allocation order so that register... · 3320e5a9
  Venkatraman Govindaraju authored May 19, 2013
  3320e5a9
- Handle i64 FrameIndex nodes in SPARC v9 mode. · ead983ce
  Jakob Stoklund Olesen authored May 19, 2013
  ead983ce
May 18, 2013
- Check InlineAsm clobbers in PPCCTRLoops · 2f474f0e
  Hal Finkel authored May 18, 2013
  2f474f0e
- AArch64: add CMake dependency to fix very parallel builds · fd2639f7
  Tim Northover authored May 18, 2013
  fd2639f7
- X86: Bad peephole interaction between adc, MOV32r0 · 5ba473af
  David Majnemer authored May 18, 2013
  5ba473af
- Add LLVMContext argument to getSetCCResultType · 75865923
  Matt Arsenault authored May 18, 2013
  75865923
- Support unaligned load/store on more ARM targets · 97b08c40
  JF Bastien authored May 17, 2013
  97b08c40
- Fix the build in c++11 mode. · 5986ce0e
  Rafael Espindola authored May 17, 2013
  5986ce0e
May 17, 2013
- R600: Lower int_load_input to copyFromReg instead of Register node · d3fcb501
  Vincent Lejeune authored May 17, 2013
  d3fcb501
- R600: Use bottom up scheduling algorithm · 3d5118ca
  Vincent Lejeune authored May 17, 2013
  3d5118ca
- R600: Use depth first scheduling algorithm · 4c81d4da
  Vincent Lejeune authored May 17, 2013
  4c81d4da
- R600: Replace big texture opcode switch in scheduler by usesTC/usesVC · e958c8e0
  Vincent Lejeune authored May 17, 2013
  e958c8e0
- R600: Relax some vector constraints on Dot4. · 519f21ee
  Vincent Lejeune authored May 17, 2013
  519f21ee
- R600: Improve texture handling · d3eed66e
  Vincent Lejeune authored May 17, 2013
  d3eed66e
- R600: Rename 128 bit registers. · 4ebef18a
  Vincent Lejeune authored May 17, 2013
  4ebef18a
- R600: Some factorization · 0fca91d5
  Vincent Lejeune authored May 17, 2013
  0fca91d5
- R600: Factorize Fetch size limit inside AMDGPUSubTarget · f9f4e1e7
  Vincent Lejeune authored May 17, 2013
  f9f4e1e7
- R600: prettier dump of clamp · 709e0168
  Vincent Lejeune authored May 17, 2013
  709e0168
- R600: Fix encoding for R600 family GPUs · ecc2ad1c
  Tom Stellard authored May 17, 2013
  ecc2ad1c
- R600: Pass MCSubtargetInfo reference to R600CodeEmitter · edade94b
  Tom Stellard authored May 17, 2013
  edade94b
- [Sparc] Implements hasReservedCallFrame and hasFP. · 641b0b5a
  Venkatraman Govindaraju authored May 17, 2013
  641b0b5a
- X86: Make shuffle -> shift conversion more aggressive about undefs. · fc33e1d9
  Benjamin Kramer authored May 17, 2013
  fc33e1d9
- · 2dbe06a9
  Ulrich Weigand authored May 17, 2013
  2dbe06a9
- · 6e23ac60
  Ulrich Weigand authored May 17, 2013
  6e23ac60
- · 994f49ed
  Ulrich Weigand authored May 17, 2013
  994f49ed
- Don't cast away constness. · 2057a2b8
  Benjamin Kramer authored May 17, 2013
  2057a2b8