llvm-svn: 320329

llvm-svn: 320328

llvm-svn: 320326

This matches AVX512 version and is more consistent overall. And improves our scheduler models.

In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses.

llvm-svn: 320325

llvm-svn: 320322

Split off some 'n' instruction versions to make it clearer when WAIT is being inserted

llvm-svn: 320321

[X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper suffix. Fix the scheduling information for some of them.

Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)'

llvm-svn: 320320

llvm-svn: 320319

llvm-svn: 320318

llvm-svn: 320317

This makes things consistent with our normal instruction naming.

llvm-svn: 320316

llvm-svn: 320315

llvm-svn: 320314

[X86] Adjust tablegen includes so we can use Instructions in scheduler models instead of just instregexs.

This separates the CPU specific scheduler model includes to occur after the instructions. Moves the instruction includes between the basic scheduler information and the CPU specific scheduler models.

llvm-svn: 320313

Follow-up for a bug that's similar to:
https://bugs.llvm.org/show_bug.cgi?id=35601

llvm-svn: 320312

llvm-svn: 320311

This should fix the larger problem with sqrt shown in:
https://bugs.llvm.org/show_bug.cgi?id=35601

llvm-svn: 320310

llvm-svn: 320309

Locally tag COPY as WriteMove, which has caused some reg-reg + reg-mem instruction tests to reorder.

llvm-svn: 320308

llvm-svn: 320307

llvm-svn: 320306

llvm-svn: 320305

We just have to locally tag COPY as WriteMove

llvm-svn: 320304

We just have to locally tag COPY as WriteMove

llvm-svn: 320303

llvm-svn: 320302

llvm-svn: 320301

We just have to locally tag COPY as WriteMove

llvm-svn: 320300

llvm-svn: 320299

CreateAddRecFromPHIWithCastsImpl() adds an IncrementNUSW overflow predicate
which allows the PSCEV rewriter to rewrite this scev expression:
 (zext i8 {0, + , (trunc i32 step to i8)} to i32)
into
 {0, +, (sext i8 (trunc i32 step to i8) to i32)}

But then it adds the wrong Equal predicate:
 %step == (zext i8 (trunc i32 %step to i8) to i32).
instead of:
 %step == (sext i8 (trunc i32 %step to i8) to i32)

This is fixed here.

Differential Revision: https://reviews.llvm.org/D40641

llvm-svn: 320298

llvm-svn: 320296

Based on the fact that the 'Y' version of the instruction is next to this, I assume Z256 is the intended value.

llvm-svn: 320295

The VEX versions were present but not the legacy SSE versions.

llvm-svn: 320294

llvm-svn: 320293

Sandy Bridge is also missing it, but it has other issues. See PR35590.

llvm-svn: 320292

[X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. Similar for all sizes of AND/OR/XOR/SUB/ADC/SBB/CMP.

llvm-svn: 320291

llvm-svn: 320290

Somehow CMPSSrr/rm was there and the VEX version was there, but this was consistently missing.

llvm-svn: 320289

llvm-svn: 320288

This adds assembly & disassembly support for the e500mc "external pid"
instructions.

See https://reviews.llvm.org/D39249.

Patch by vit9696 <vit9696@avp.su>

llvm-svn: 320287

llvm-svn: 320285