Commits · fa9439fac84ea4eb4050aa1ae150c0ec2cf86c20 · Lorenzo Albano / LLVM bpEVL · GitLab

Feb 27, 2020
- [AArch64][SVE] Add intrinsics for first-faulting gather loads · fa9439fa
  Andrzej Warzynski authored Feb 21, 2020
  fa9439fa
- [ARM] Fixup FP16 bitcasts · 13f2a588
  David Green authored Feb 25, 2020
  13f2a588
- [MC][ARM] Resolve some pcrel fixups at assembly time (PR44929) · 2e24219d
  Hans Wennborg authored Feb 27, 2020
  2e24219d
- Revert "[Hexagon] Improve casting of boolean HVX vectors to scalars" · 01472841
  Kirill Bobyrev authored Feb 27, 2020
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- [DebugInfo][ARM] Fix noreg case when checkig if it is an addImm · 58d9e819
  Djordje Todorovic authored Feb 27, 2020
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- [ARM] Add CPSR as an implicit use of t2IT · e58229fd
  Sam Parker authored Feb 27, 2020
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- [AArch64] Peephole optimization: merge AND and TST instructions · 13db7490
  Sjoerd Meijer authored Feb 27, 2020
  13db7490
- [X86] Add proper MachinePointerInfo to stack store created in LowerWin64_i128OP. · 82a21c16
  Craig Topper authored Feb 26, 2020
  
  82a21c16
- [X86] Explicitly pass Destination VT and debug location to BuildFILD. NFC · 870363a2
  Craig Topper authored Feb 26, 2020
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- [X86] Explicitly pass Pointer, MachinePointerInfo and Alignment to BuildFILD. · 15e2831f
  Craig Topper authored Feb 26, 2020
  15e2831f
Feb 26, 2020
- [X86] Query constant pool object alignment instead of hardcoding. · 77d9b7b2
  Craig Topper authored Feb 26, 2020
  
  77d9b7b2
- [X86] Use proper alignment for stack temporary and correct MachinePointerInfo... · 9c1a707b
  Craig Topper authored Feb 26, 2020
  9c1a707b
- [X86] Use correct MachineMemOperand for stack load in LowerFLT_ROUNDS_ · a8186935
  Craig Topper authored Feb 26, 2020
  
  a8186935
- [X86] Add proper MachinePointerInfo to the loads/stores created for moving... · 14306ce8
  Craig Topper authored Feb 26, 2020
  14306ce8
- [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection. · 65f99b53
  Amara Emerson authored Feb 24, 2020
  65f99b53
- [ms] Rename ParsingInlineAsm functions/variables to reflect MS-specificity. · 85b641c2
  Eric Astor authored Feb 26, 2020
  85b641c2
- [AVR] Fix private label prefix · 6afc3de4
  Ayke van Laethem authored Feb 25, 2020
  6afc3de4
- [AVR] Don't adjust addresses by 2 for absolute values · 165f707f
  Ayke van Laethem authored Feb 07, 2020
  165f707f
- [Hexagon] Improve casting of boolean HVX vectors to scalars · 7691790d
  Krzysztof Parzyszek authored Feb 26, 2020
  7691790d
- [SDAG] Add SDNode::values() = make_range(values_begin(), values_end()) · fd7c2e24
  Krzysztof Parzyszek authored Feb 26, 2020
  fd7c2e24
- Avoid SmallString.h include in MD5.h, NFC · 465dca79
  Reid Kleckner authored Feb 26, 2020
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- Full fix for "AMDGPU/SIInsertSkips: Fix the determination of whether... · d6b05fcc
  Nicolai Hähnle authored Feb 26, 2020
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- [ARM,MVE] Add predicated intrinsics for many unary functions. · 9eb3cc10
  Simon Tatham authored Feb 26, 2020
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- [AIX] Remove whitelist checking for ExternalSymbolSDNodes · e7375e99
  Xiangling Liao authored Feb 26, 2020
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- Quick fix for bot failure on "AMDGPU/SIInsertSkips: Fix the determination of... · 0aec4b41
  Nicolai Hähnle authored Feb 26, 2020
  0aec4b41
- AMDGPU/SIInsertSkips: Fix the determination of whether early-exit-after-kill is possible · 0f1df489
  Nicolai Hähnle authored Feb 21, 2020
  0f1df489
- [AArch64][SVE] Add SVE2 intrinsics for bit permutation & table lookup · 9c859fc5
  Kerry McLaughlin authored Feb 26, 2020
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- [ARM][RDA] add getUniqueReachingMIDef · 1d06e75d
  Sam Parker authored Feb 26, 2020
  1d06e75d
- [AArch64] Flip default for register renaming in the ld/st optimizier. · a059be72
  Florian Hahn authored Feb 26, 2020
  a059be72
- [ARC][NFC] Remove trailing space · f6603aed
  Jim Lin authored Feb 25, 2020
  
  f6603aed
- [PowerPC] Fix the unexpected modification caused by D62993 in LowerSELECT_CC for power9 · b083d7a3
  Kang Zhang authored Feb 26, 2020
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- [MC][ARM] Don't create multiple .ARM.exidx associated to one .text · d0c4277d
  Fangrui Song authored Feb 24, 2020
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- [SelectionDAG][PowerPC][AArch64][X86][ARM] Add chain input and output the ISD::FLT_ROUNDS_ · 735d27dc
  Craig Topper authored Feb 25, 2020
  735d27dc
Feb 25, 2020
- Revert "[X86MCTargetDesc.h] Speculative fix for macro collision with sys/param.h" · 8594f3d8
  Vedant Kumar authored Feb 25, 2020
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- [WebAssembly] Simplify extract_vector lowering · 0906dca4
  Thomas Lively authored Feb 21, 2020
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- [NFC][SCEV] Piping to pass TTI into SCEVExpander::isHighCostExpansionHelper() · 0789f280
  Roman Lebedev authored Feb 25, 2020
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- [AMDGPU] Implement wave64 DWARF register mapping · 481b1c83
  Scott Linder authored Nov 08, 2019
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- [X86MCTargetDesc.h] Speculative fix for macro collision with sys/param.h · eee22ec3
  Vedant Kumar authored Feb 25, 2020
  eee22ec3
- AMDGPU/GlobalISel: Use packed for G_ADD/G_SUB/G_MUL v2s16 · 86e13ec1
  Matt Arsenault authored Feb 17, 2020
  
  86e13ec1
- AMDGPU/GlobalISel: Legalize s64 min/max by lowering · 33cbd5ee
  Jay Foad authored Feb 25, 2020
  33cbd5ee