X86InstrInfo.td

                  "fld $src">, D9;
def FLD32m  : FPI<0xD9, MRM0m, ZeroArgFP,
                  (ops f32mem:$src, variable_ops),
                  "fld{s} $src">;
def FLD64m  : FPI<0xDD, MRM0m, ZeroArgFP,
                  (ops f64mem:$src, variable_ops),
                  "fld{l} $src">;
def FLD80m  : FPI<0xDB, MRM5m, ZeroArgFP,
                  (ops f80mem:$src, variable_ops),
                  "fld{t} $src">;
def FILD16m : FPI<0xDF, MRM0m, ZeroArgFP,
                  (ops i16mem:$src, variable_ops),
                  "fild{s} $src">;
def FILD32m : FPI<0xDB, MRM0m, ZeroArgFP,
                  (ops i32mem:$src, variable_ops),
                  "fild{l} $src">;
def FILD64m : FPI<0xDF, MRM5m, ZeroArgFP,
                  (ops i64mem:$src, variable_ops),
                  "fild{ll} $src">;

def FSTrr    : FPI<0xD0, AddRegFrm, NotFP,
                   (ops RST:$op, variable_ops),
                   "fst $op">, DD;
def FSTPrr   : FPI<0xD8, AddRegFrm, NotFP,
                   (ops RST:$op, variable_ops),
                   "fstp $op">, DD;
def FST32m   : FPI<0xD9, MRM2m, OneArgFP,
                   (ops f32mem:$op, variable_ops),
                   "fst{s} $op">;
def FST64m   : FPI<0xDD, MRM2m, OneArgFP,
                   (ops f64mem:$op, variable_ops),
                   "fst{l} $op">;
def FSTP32m  : FPI<0xD9, MRM3m, OneArgFP,
                   (ops f32mem:$op, variable_ops),
                   "fstp{s} $op">;
def FSTP64m  : FPI<0xDD, MRM3m, OneArgFP,
                   (ops f64mem:$op, variable_ops),
                   "fstp{l} $op">;
def FSTP80m  : FPI<0xDB, MRM7m, OneArgFP,
                   (ops f80mem:$op, variable_ops),
                   "fstp{t} $op">;

def FIST16m  : FPI<0xDF, MRM2m , OneArgFP,
                   (ops i16mem:$op, variable_ops),
                   "fist{s} $op">;
def FIST32m  : FPI<0xDB, MRM2m , OneArgFP,
                   (ops i32mem:$op, variable_ops),
                   "fist{l} $op">;
def FISTP16m : FPI<0xDF, MRM3m , NotFP   ,
                   (ops i16mem:$op, variable_ops),
                   "fistp{s} $op">;
def FISTP32m : FPI<0xDB, MRM3m , NotFP   ,
                   (ops i32mem:$op, variable_ops),
                   "fistp{l} $op">;
def FISTP64m : FPI<0xDF, MRM7m , OneArgFP,
                   (ops i64mem:$op, variable_ops),
                   "fistp{ll} $op">;

def FXCH     : FPI<0xC8, AddRegFrm, NotFP,
                   (ops RST:$op), "fxch $op">, D9;      // fxch ST(i), ST(0)

// Floating point constant loads...
def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP, (ops variable_ops), "fldz">, D9;
def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP, (ops variable_ops), "fld1">, D9;


// Unary operations...
def FCHS  : FPI<0xE0, RawFrm, OneArgFPRW,   // f1 = fchs f2
                (ops variable_ops),
                "fchs">, D9;
def FABS  : FPI<0xE1, RawFrm, OneArgFPRW,   // f1 = fabs f2
                (ops variable_ops),
                "fabs">, D9;
def FSQRT : FPI<0xFA, RawFrm, OneArgFPRW,   // fsqrt ST(0)
                (ops variable_ops),
                "fsqrt">, D9;
def FSIN  : FPI<0xFE, RawFrm, OneArgFPRW,   // fsin  ST(0)
                (ops variable_ops),
                "fsin">, D9;
def FCOS  : FPI<0xFF, RawFrm, OneArgFPRW,   // fcos  ST(0)
                (ops variable_ops),
                "fcos">, D9;
def FTST  : FPI<0xE4, RawFrm, OneArgFP  ,   // ftst ST(0)
                (ops variable_ops),
                "ftst">, D9;

// Binary arithmetic operations...
class FPST0rInst<bits<8> o, dag ops, string asm>
  : I<o, AddRegFrm, ops, asm, []>, D8 {
  list<Register> Uses = [ST0];
  list<Register> Defs = [ST0];
}
class FPrST0Inst<bits<8> o, dag ops, string asm>
  : I<o, AddRegFrm, ops, asm, []>, DC {
  list<Register> Uses = [ST0];
}
class FPrST0PInst<bits<8> o, dag ops, string asm>
  : I<o, AddRegFrm, ops, asm, []>, DE {
  list<Register> Uses = [ST0];
}

def FADDST0r   : FPST0rInst <0xC0, (ops RST:$op),
                             "fadd $op">;
def FADDrST0   : FPrST0Inst <0xC0, (ops RST:$op),
                             "fadd {%ST(0), $op|$op, %ST(0)}">;
def FADDPrST0  : FPrST0PInst<0xC0, (ops RST:$op),
                             "faddp $op">;

// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
// of some of the 'reverse' forms of the fsub and fdiv instructions.  As such,
// we have to put some 'r's in and take them out of weird places.
def FSUBRST0r  : FPST0rInst <0xE8, (ops RST:$op),
                             "fsubr $op">;
def FSUBrST0   : FPrST0Inst <0xE8, (ops RST:$op),
                             "fsub{r} {%ST(0), $op|$op, %ST(0)}">;
def FSUBPrST0  : FPrST0PInst<0xE8, (ops RST:$op),
                             "fsub{r}p $op">;

def FSUBST0r   : FPST0rInst <0xE0, (ops RST:$op),
                             "fsub $op">;
def FSUBRrST0  : FPrST0Inst <0xE0, (ops RST:$op),
                             "fsub{|r} {%ST(0), $op|$op, %ST(0)}">;
def FSUBRPrST0 : FPrST0PInst<0xE0, (ops RST:$op),
                             "fsub{|r}p $op">;

def FMULST0r   : FPST0rInst <0xC8, (ops RST:$op),
                             "fmul $op">;
def FMULrST0   : FPrST0Inst <0xC8, (ops RST:$op),
                             "fmul {%ST(0), $op|$op, %ST(0)}">;
def FMULPrST0  : FPrST0PInst<0xC8, (ops RST:$op),
                             "fmulp $op">;

def FDIVRST0r  : FPST0rInst <0xF8, (ops RST:$op),
                             "fdivr $op">;
def FDIVrST0   : FPrST0Inst <0xF8, (ops RST:$op),
                             "fdiv{r} {%ST(0), $op|$op, %ST(0)}">;
def FDIVPrST0  : FPrST0PInst<0xF8, (ops RST:$op),
                             "fdiv{r}p $op">;

def FDIVST0r   : FPST0rInst <0xF0, (ops RST:$op),  // ST(0) = ST(0) / ST(i)
                             "fdiv $op">;
def FDIVRrST0  : FPrST0Inst <0xF0, (ops RST:$op),  // ST(i) = ST(0) / ST(i)
                             "fdiv{|r} {%ST(0), $op|$op, %ST(0)}">;
def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op),  // ST(i) = ST(0) / ST(i), pop
                             "fdiv{|r}p $op">;

// Floating point compares
def FUCOMr    : FPI<0xE0, AddRegFrm, CompareFP,   // FPSW = cmp ST(0) with ST(i)
                    (ops RST:$reg, variable_ops),
                    "fucom $reg">, DD, Imp<[ST0],[]>;
def FUCOMPr   : I<0xE8, AddRegFrm,           // FPSW = cmp ST(0) with ST(i), pop
                  (ops RST:$reg, variable_ops),
                  "fucomp $reg", []>, DD, Imp<[ST0],[]>;
def FUCOMPPr  : I<0xE9, RawFrm,                // cmp ST(0) with ST(1), pop, pop
                  (ops variable_ops),
                  "fucompp", []>, DA, Imp<[ST0],[]>;

def FUCOMIr  : FPI<0xE8, AddRegFrm, CompareFP,  // CC = cmp ST(0) with ST(i)
                   (ops RST:$reg, variable_ops),
                   "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
def FUCOMIPr : I<0xE8, AddRegFrm,              // CC = cmp ST(0) with ST(i), pop
                 (ops RST:$reg, variable_ops),
                 "fucomip {$reg, %ST(0)|%ST(0), $reg}", []>, DF, Imp<[ST0],[]>;


// Floating point flag ops
def FNSTSW8r  : I<0xE0, RawFrm,                  // AX = fp flags
                  (ops), "fnstsw", []>, DF, Imp<[],[AX]>;

def FNSTCW16m : I<0xD9, MRM7m,                   // [mem16] = X87 control world
                  (ops i16mem:$dst), "fnstcw $dst", []>;
def FLDCW16m  : I<0xD9, MRM5m,                   // X87 control world = [mem16]
                  (ops i16mem:$dst), "fldcw $dst", []>;