HexagonInstrInfo.td

//==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the Hexagon instructions in TableGen format.
//
//===----------------------------------------------------------------------===//

include "HexagonInstrFormats.td"
include "HexagonOperands.td"

// Multi-class for logical operators.
multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
  def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
                 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
                 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
                                                   (i32 IntRegs:$c)))]>;
  def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
                 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
                 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
                                                   (i32 IntRegs:$c)))]>;
}

// Multi-class for compare ops.
let isCompare = 1 in {
multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
  def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
                 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
                 [(set (i1 PredRegs:$dst),
                       (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
}
multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
  def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
                 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
                 [(set (i1 PredRegs:$dst),
                       (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
}

multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
  let CextOpcode = CextOp in {
    let InputType = "reg" in
    def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
                   !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
                   [(set (i1 PredRegs:$dst),
                         (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;

    let isExtendable = 1, opExtendable = 2, isExtentSigned = 1,
    opExtentBits = 10, InputType = "imm" in
    def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
                   !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
                   [(set (i1 PredRegs:$dst),
                         (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
  }
}

multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
  let CextOpcode = CextOp in {
    let InputType = "reg" in
    def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
                   !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
                   [(set (i1 PredRegs:$dst),
                         (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;

    let isExtendable = 1, opExtendable = 2, isExtentSigned = 0,
    opExtentBits = 9, InputType = "imm" in
    def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
                   !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
                   [(set (i1 PredRegs:$dst),
                         (OpNode (i32 IntRegs:$b), u9ExtPred:$c))]>;
  }
}

multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
  def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Ext:$c),
                 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
                 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
                                                   u8ExtPred:$c))]>;
}

multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
  def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
                 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
                 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
                                                   s8ExtPred:$c))]>;
}
}

//===----------------------------------------------------------------------===//
// ALU32/ALU (Instructions with register-register form)
//===----------------------------------------------------------------------===//
multiclass ALU32_Pbase<string mnemonic, bit isNot,
                       bit isPredNew> {

  let PNewValue = !if(isPredNew, "new", "") in
  def NAME : ALU32_rr<(outs IntRegs:$dst),
            (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
            !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
            ") $dst = ")#mnemonic#"($src2, $src3)",
            []>;
}

multiclass ALU32_Pred<string mnemonic, bit PredNot> {
  let PredSense = !if(PredNot, "false", "true") in {
    defm _c#NAME : ALU32_Pbase<mnemonic, PredNot, 0>;
    // Predicate new
    defm _cdn#NAME : ALU32_Pbase<mnemonic, PredNot, 1>;
  }
}

let InputType = "reg" in
multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
  let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
    let isPredicable = 1 in
    def NAME : ALU32_rr<(outs IntRegs:$dst),
            (ins IntRegs:$src1, IntRegs:$src2),
            "$dst = "#mnemonic#"($src1, $src2)",
            [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
                                              (i32 IntRegs:$src2)))]>;

    let neverHasSideEffects = 1, isPredicated = 1 in {
      defm Pt : ALU32_Pred<mnemonic, 0>;
      defm NotPt : ALU32_Pred<mnemonic, 1>;
    }
  }
}

let isCommutable = 1 in {
  defm ADD_rr : ALU32_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
  defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
  defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
  defm OR_rr  : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
}

defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;

//===----------------------------------------------------------------------===//
// ALU32/ALU (ADD with register-immediate form)
//===----------------------------------------------------------------------===//
multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
  let PNewValue = !if(isPredNew, "new", "") in
  def NAME : ALU32_ri<(outs IntRegs:$dst),
            (ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
            !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
            ") $dst = ")#mnemonic#"($src2, #$src3)",
            []>;
}

multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
  let PredSense = !if(PredNot, "false", "true") in {
    defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
    // Predicate new
    defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
  }
}

let isExtendable = 1, InputType = "imm" in
multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
  let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
    let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
    isPredicable = 1 in
    def NAME : ALU32_ri<(outs IntRegs:$dst),
            (ins IntRegs:$src1, s16Ext:$src2),
            "$dst = "#mnemonic#"($src1, #$src2)",
            [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
                                              (s16ExtPred:$src2)))]>;

    let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
    neverHasSideEffects = 1, isPredicated = 1 in {
      defm Pt : ALU32ri_Pred<mnemonic, 0>;
      defm NotPt : ALU32ri_Pred<mnemonic, 1>;
    }
  }
}

defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;

let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
CextOpcode = "OR", InputType = "imm" in
def OR_ri : ALU32_ri<(outs IntRegs:$dst),
            (ins IntRegs:$src1, s10Ext:$src2),
            "$dst = or($src1, #$src2)",
            [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
                                          s10ExtPred:$src2))]>, ImmRegRel;

def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
            (ins IntRegs:$src1),
            "$dst = not($src1)",
            [(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;

let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
InputType = "imm", CextOpcode = "AND" in
def AND_ri : ALU32_ri<(outs IntRegs:$dst),
            (ins IntRegs:$src1, s10Ext:$src2),
            "$dst = and($src1, #$src2)",
            [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
                                           s10ExtPred:$src2))]>, ImmRegRel;
// Negate.
def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
          "$dst = neg($src1)",
          [(set (i32 IntRegs:$dst), (ineg (i32 IntRegs:$src1)))]>;
// Nop.
let neverHasSideEffects = 1 in
def NOP : ALU32_rr<(outs), (ins),
          "nop",
          []>;

// Rd32=sub(#s10,Rs32)
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
CextOpcode = "SUB", InputType = "imm" in
def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
            (ins s10Ext:$src1, IntRegs:$src2),
            "$dst = sub(#$src1, $src2)",
            [(set IntRegs:$dst, (sub s10ExtPred:$src1, IntRegs:$src2))]>,
            ImmRegRel;


multiclass TFR_Pred<bit PredNot> {
  let PredSense = !if(PredNot, "false", "true") in {
    def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
                           (ins PredRegs:$src1, IntRegs:$src2),
            !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
            []>;
    // Predicate new
    let PNewValue = "new" in
    def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
                             (ins PredRegs:$src1, IntRegs:$src2),
            !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
            []>;
  }
}

let InputType = "reg", neverHasSideEffects = 1 in
multiclass TFR_base<string CextOp> {
  let CextOpcode = CextOp, BaseOpcode = CextOp in {
    let isPredicable = 1 in
    def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
            "$dst = $src1",
            []>;

    let  isPredicated = 1 in {
      defm Pt : TFR_Pred<0>;
      defm NotPt : TFR_Pred<1>;
    }
  }
}

multiclass TFR64_Pred<bit PredNot> {
  let PredSense = !if(PredNot, "false", "true") in {
    def _c#NAME : ALU32_rr<(outs DoubleRegs:$dst),
                           (ins PredRegs:$src1, DoubleRegs:$src2),
            !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
            []>;
    // Predicate new
    let PNewValue = "new" in
    def _cdn#NAME : ALU32_rr<(outs DoubleRegs:$dst),
                             (ins PredRegs:$src1, DoubleRegs:$src2),
            !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
            []>;
  }
}

let InputType = "reg", neverHasSideEffects = 1 in
multiclass TFR64_base<string CextOp> {
  let CextOpcode = CextOp, BaseOpcode = CextOp in {
    let isPredicable = 1 in
    def NAME : ALU32_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
            "$dst = $src1",
            []>;

    let  isPredicated = 1 in {
      defm Pt : TFR64_Pred<0>;
      defm NotPt : TFR64_Pred<1>;
    }
  }
}


multiclass TFRI_Pred<bit PredNot> {
  let PredSense = !if(PredNot, "false", "true") in {
    def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
                           (ins PredRegs:$src1, s12Ext:$src2),
            !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
            []>;

    // Predicate new
    let PNewValue = "new" in
    def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
                             (ins PredRegs:$src1, s12Ext:$src2),
            !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
            []>;
  }
}

let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
multiclass TFRI_base<string CextOp> {
  let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
    let opExtendable = 1, opExtentBits = 16, isMoveImm = 1, isPredicable = 1,
    isReMaterializable = 1 in
    def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
            "$dst = #$src1",
            [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;

    let opExtendable = 2,  opExtentBits = 12, neverHasSideEffects = 1,
    isPredicated = 1 in {
      defm Pt    : TFRI_Pred<0>;
      defm NotPt : TFRI_Pred<1>;
    }
  }
}

defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
defm TFR64 : TFR64_base<"TFR64">, ImmRegRel, PredNewRel;

// Transfer control register.
let neverHasSideEffects = 1 in
def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
           "$dst = $src1",
           []>;
//===----------------------------------------------------------------------===//
// ALU32/ALU -
//===----------------------------------------------------------------------===//


//===----------------------------------------------------------------------===//
// ALU32/PERM +
//===----------------------------------------------------------------------===//

// Combine.

def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
  [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;

def HexagonWrapperCombineII :
  SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
def HexagonWrapperCombineRR :
  SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;

// Combines the two integer registers SRC1 and SRC2 into a double register.
let isPredicable = 1 in
def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1,
                                                       IntRegs:$src2),
  "$dst = combine($src1, $src2)",
  [(set (i64 DoubleRegs:$dst),
        (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
                                      (i32 IntRegs:$src2))))]>;

// Rd=combine(Rt.[HL], Rs.[HL])
class COMBINE_halves<string A, string B>: ALU32_rr<(outs IntRegs:$dst),
                                                   (ins IntRegs:$src1,
                                                        IntRegs:$src2),
  "$dst = combine($src1."# A #", $src2."# B #")", []>;

let isPredicable = 1 in {
  def COMBINE_hh : COMBINE_halves<"H", "H">;
  def COMBINE_hl : COMBINE_halves<"H", "L">;
  def COMBINE_lh : COMBINE_halves<"L", "H">;
  def COMBINE_ll : COMBINE_halves<"L", "L">;
}

def : Pat<(i32 (trunc (i64 (srl (i64 DoubleRegs:$a), (i32 16))))),
  (COMBINE_lh (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_hireg),
              (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_loreg))>;

// Combines the two immediates SRC1 and SRC2 into a double register.
class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
  ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
  "$dst = combine(#$src1, #$src2)",
  [(set (i64 DoubleRegs:$dst),
        (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;

let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;

// Mux.
def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
                                                   DoubleRegs:$src2,
                                                   DoubleRegs:$src3),
            "$dst = vmux($src1, $src2, $src3)",
            []>;

let CextOpcode = "MUX", InputType = "reg" in
def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
                                            IntRegs:$src2, IntRegs:$src3),
             "$dst = mux($src1, $src2, $src3)",
             [(set (i32 IntRegs:$dst),
                   (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
                                (i32 IntRegs:$src3))))]>, ImmRegRel;

let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
CextOpcode = "MUX", InputType = "imm" in
def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
                                                IntRegs:$src3),
             "$dst = mux($src1, #$src2, $src3)",
             [(set (i32 IntRegs:$dst),
                   (i32 (select (i1 PredRegs:$src1), s8ExtPred:$src2,
                                (i32 IntRegs:$src3))))]>, ImmRegRel;

let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
CextOpcode = "MUX", InputType = "imm" in
def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
                                                s8Ext:$src3),
             "$dst = mux($src1, $src2, #$src3)",
             [(set (i32 IntRegs:$dst),
                   (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
                                 s8ExtPred:$src3)))]>, ImmRegRel;

let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
                                                s8Imm:$src3),
             "$dst = mux($src1, #$src2, #$src3)",
             [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
                                                    s8ExtPred:$src2,
                                                    s8ImmPred:$src3)))]>;

// Shift halfword.
let isPredicable = 1 in
def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
           "$dst = aslh($src1)",
           [(set (i32 IntRegs:$dst), (shl 16, (i32 IntRegs:$src1)))]>;

let isPredicable = 1 in
def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
           "$dst = asrh($src1)",
           [(set (i32 IntRegs:$dst), (sra 16, (i32 IntRegs:$src1)))]>;

// Sign extend.
let isPredicable = 1 in
def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
           "$dst = sxtb($src1)",
           [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i8))]>;

let isPredicable = 1 in
def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
           "$dst = sxth($src1)",
           [(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i16))]>;

// Zero extend.
let isPredicable = 1, neverHasSideEffects = 1 in
def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
           "$dst = zxtb($src1)",
           []>;

let isPredicable = 1, neverHasSideEffects = 1 in
def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
                    "$dst = zxth($src1)",
                    []>;
//===----------------------------------------------------------------------===//
// ALU32/PERM -
//===----------------------------------------------------------------------===//


//===----------------------------------------------------------------------===//
// ALU32/PRED +
//===----------------------------------------------------------------------===//

// Conditional combine.
let neverHasSideEffects = 1, isPredicated = 1 in
def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
            (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
            "if ($src1) $dst = combine($src2, $src3)",
            []>;

let neverHasSideEffects = 1, isPredicated = 1 in
def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
            (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
            "if (!$src1) $dst = combine($src2, $src3)",
            []>;

let neverHasSideEffects = 1, isPredicated = 1 in
def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
            (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
            "if ($src1.new) $dst = combine($src2, $src3)",
            []>;

let neverHasSideEffects = 1, isPredicated = 1 in
def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
            (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
            "if (!$src1.new) $dst = combine($src2, $src3)",
            []>;

// Compare.
defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel;
defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel;
defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", "CMPEQ", seteq>, ImmRegRel;
defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;

def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
    "$dst = cl0($src1)",
    [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;

def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
    "$dst = ct0($src1)",
    [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;

def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
    "$dst = cl0($src1)",
    [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;

def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
    "$dst = ct0($src1)",
    [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;

def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
    "$dst = tstbit($src1, $src2)",
    [(set (i1 PredRegs:$dst),
          (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;

def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
    "$dst = tstbit($src1, $src2)",
    [(set (i1 PredRegs:$dst),
          (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;

//===----------------------------------------------------------------------===//
// ALU32/PRED -
//===----------------------------------------------------------------------===//


//===----------------------------------------------------------------------===//
// ALU64/ALU +
//===----------------------------------------------------------------------===//
// Add.
def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
                                                     DoubleRegs:$src2),
               "$dst = add($src1, $src2)",
               [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
                                                 (i64 DoubleRegs:$src2)))]>;

// Add halfword.

// Compare.
defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;

// Logical operations.
def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
                                                     DoubleRegs:$src2),
               "$dst = and($src1, $src2)",
               [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
                                                 (i64 DoubleRegs:$src2)))]>;

def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
                                                    DoubleRegs:$src2),
              "$dst = or($src1, $src2)",
              [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
                                               (i64 DoubleRegs:$src2)))]>;

def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
                                                     DoubleRegs:$src2),
               "$dst = xor($src1, $src2)",
               [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
                                                 (i64 DoubleRegs:$src2)))]>;

// Maximum.
def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
              "$dst = max($src2, $src1)",
              [(set (i32 IntRegs:$dst),
                    (i32 (select (i1 (setlt (i32 IntRegs:$src2),
                                            (i32 IntRegs:$src1))),
                                 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;

def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
              "$dst = maxu($src2, $src1)",
              [(set (i32 IntRegs:$dst),
                    (i32 (select (i1 (setult (i32 IntRegs:$src2),
                                             (i32 IntRegs:$src1))),
                                 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;

def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
                                                    DoubleRegs:$src2),
              "$dst = max($src2, $src1)",
              [(set (i64 DoubleRegs:$dst),
                    (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
                                            (i64 DoubleRegs:$src1))),
                                 (i64 DoubleRegs:$src1),
                                 (i64 DoubleRegs:$src2))))]>;

def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
                                                     DoubleRegs:$src2),
              "$dst = maxu($src2, $src1)",
              [(set (i64 DoubleRegs:$dst),
                    (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
                                             (i64 DoubleRegs:$src1))),
                                 (i64 DoubleRegs:$src1),
                                 (i64 DoubleRegs:$src2))))]>;

// Minimum.
def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
              "$dst = min($src2, $src1)",
              [(set (i32 IntRegs:$dst),
                    (i32 (select (i1 (setgt (i32 IntRegs:$src2),
                                            (i32 IntRegs:$src1))),
                                 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;

def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
              "$dst = minu($src2, $src1)",
              [(set (i32 IntRegs:$dst),
                    (i32 (select (i1 (setugt (i32 IntRegs:$src2),
                                             (i32 IntRegs:$src1))),
                                 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;

def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
                                                    DoubleRegs:$src2),
              "$dst = min($src2, $src1)",
              [(set (i64 DoubleRegs:$dst),
                    (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
                                            (i64 DoubleRegs:$src1))),
                                 (i64 DoubleRegs:$src1),
                                 (i64 DoubleRegs:$src2))))]>;

def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
                                                     DoubleRegs:$src2),
              "$dst = minu($src2, $src1)",
              [(set (i64 DoubleRegs:$dst),
                    (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
                                             (i64 DoubleRegs:$src1))),
                                 (i64 DoubleRegs:$src1),
                                 (i64 DoubleRegs:$src2))))]>;

// Subtract.
def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
                                                     DoubleRegs:$src2),
               "$dst = sub($src1, $src2)",
               [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
                                                 (i64 DoubleRegs:$src2)))]>;

// Subtract halfword.

//===----------------------------------------------------------------------===//
// ALU64/ALU -
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// ALU64/BIT +
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
// ALU64/BIT -
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// ALU64/PERM +
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
// ALU64/PERM -
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// CR +
//===----------------------------------------------------------------------===//
// Logical reductions on predicates.

// Looping instructions.

// Pipelined looping instructions.

// Logical operations on predicates.
def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
             "$dst = and($src1, $src2)",
             [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
                                            (i1 PredRegs:$src2)))]>;

let neverHasSideEffects = 1 in
def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
                                                 PredRegs:$src2),
                "$dst = and($src1, !$src2)",
                []>;

def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
             "$dst = any8($src1)",
             []>;

def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
             "$dst = all8($src1)",
             []>;

def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
                                                 PredRegs:$src2),
             "$dst = vitpack($src1, $src2)",
             []>;

def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
                                                    DoubleRegs:$src2,
                                                    PredRegs:$src3),
             "$dst = valignb($src1, $src2, $src3)",
             []>;

def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
                                                     DoubleRegs:$src2,
                                                     PredRegs:$src3),
             "$dst = vspliceb($src1, $src2, $src3)",
             []>;

def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
             "$dst = mask($src1)",
             []>;

def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
             "$dst = not($src1)",
             [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;

def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
            "$dst = or($src1, $src2)",
            [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
                                          (i1 PredRegs:$src2)))]>;

def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
             "$dst = xor($src1, $src2)",
             [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
                                            (i1 PredRegs:$src2)))]>;


// User control register transfer.
//===----------------------------------------------------------------------===//
// CR -
//===----------------------------------------------------------------------===//


//===----------------------------------------------------------------------===//
// J +
//===----------------------------------------------------------------------===//
// Jump to address.
let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
  def JMP : JInst< (outs),
            (ins brtarget:$offset),
            "jump $offset",
            [(br bb:$offset)]>;
}

// if (p0) jump
let isBranch = 1, isTerminator=1, Defs = [PC],
    isPredicated = 1 in {
  def JMP_c : JInst< (outs),
                 (ins PredRegs:$src, brtarget:$offset),
                 "if ($src) jump $offset",
                 [(brcond (i1 PredRegs:$src), bb:$offset)]>;
}

// if (!p0) jump
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
    isPredicated = 1 in {
  def JMP_cNot : JInst< (outs),
                    (ins PredRegs:$src, brtarget:$offset),
                    "if (!$src) jump $offset",
                    []>;
}

let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
    isPredicated = 1 in {
  def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
               "if ($pred) jump $dst",
               []>;
}

// Jump to address conditioned on new predicate.
// if (p0) jump:t
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
    isPredicated = 1 in {
  def JMP_cdnPt : JInst< (outs),
                   (ins PredRegs:$src, brtarget:$offset),
                   "if ($src.new) jump:t $offset",
                   []>;
}

// if (!p0) jump:t
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
    isPredicated = 1 in {
  def JMP_cdnNotPt : JInst< (outs),
                      (ins PredRegs:$src, brtarget:$offset),
                      "if (!$src.new) jump:t $offset",
                      []>;
}

// Not taken.
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
    isPredicated = 1 in {
  def JMP_cdnPnt : JInst< (outs),
                    (ins PredRegs:$src, brtarget:$offset),
                    "if ($src.new) jump:nt $offset",
                    []>;
}

// Not taken.
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
    isPredicated = 1 in {
  def JMP_cdnNotPnt : JInst< (outs),
                       (ins PredRegs:$src, brtarget:$offset),
                       "if (!$src.new) jump:nt $offset",
                       []>;
}
//===----------------------------------------------------------------------===//
// J -
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// JR +
//===----------------------------------------------------------------------===//
def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
                               [SDNPHasChain, SDNPOptInGlue]>;

// Jump to address from register.
let isPredicable =1, isReturn = 1, isTerminator = 1, isBarrier = 1,
  Defs = [PC], Uses = [R31] in {
  def JMPR: JRInst<(outs), (ins),
                   "jumpr r31",
                   [(retflag)]>;
}

// Jump to address from register.
let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
  Defs = [PC], Uses = [R31] in {
  def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
                       "if ($src1) jumpr r31",
                       []>;
}

// Jump to address from register.
let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
  Defs = [PC], Uses = [R31] in {
  def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
                          "if (!$src1) jumpr r31",
                          []>;
}

//===----------------------------------------------------------------------===//
// JR -
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// LD +
//===----------------------------------------------------------------------===//
///
// Load -- MEMri operand
multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
                          bit isNot, bit isPredNew> {
  let PNewValue = !if(isPredNew, "new", "") in
  def NAME : LDInst2<(outs RC:$dst),
                       (ins PredRegs:$src1, MEMri:$addr),
            !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
            ") ")#"$dst = "#mnemonic#"($addr)",
            []>;
}

multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
  let PredSense = !if(PredNot, "false", "true") in {
    defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
    // Predicate new
    defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
  }
}

let isExtendable = 1, neverHasSideEffects = 1 in
multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
                    bits<5> ImmBits, bits<5> PredImmBits> {

  let CextOpcode = CextOp, BaseOpcode = CextOp in {
    let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
        isPredicable = 1 in
      def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
                   "$dst = "#mnemonic#"($addr)",
                   []>;

    let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
        isPredicated = 1 in {
      defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
      defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
    }
  }
}

let addrMode = BaseImmOffset, isMEMri = "true" in {
  defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
  defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
  defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
  defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
  defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
  defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
}

def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
            (LDrib ADDRriS11_0:$addr) >;

def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
            (LDriub ADDRriS11_0:$addr) >;

def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
            (LDrih ADDRriS11_1:$addr) >;

def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
            (LDriuh ADDRriS11_1:$addr) >;

def : Pat < (i32 (load ADDRriS11_2:$addr)),
            (LDriw ADDRriS11_2:$addr) >;

def : Pat < (i64 (load ADDRriS11_3:$addr)),
            (LDrid ADDRriS11_3:$addr) >;


// Load - Base with Immediate offset addressing mode
multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
                        bit isNot, bit isPredNew> {
  let PNewValue = !if(isPredNew, "new", "") in
  def NAME : LDInst2<(outs RC:$dst),
                     (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
            !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
            ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
            []>;
}

multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
                        bit PredNot> {
  let PredSense = !if(PredNot, "false", "true") in {
    defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
    // Predicate new
    defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
  }
}

let isExtendable = 1, neverHasSideEffects = 1 in
multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
                   Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
                   bits<5> PredImmBits> {

  let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
    let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
        isPredicable = 1, AddedComplexity = 20 in
      def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
                   "$dst = "#mnemonic#"($src1+#$offset)",
                   []>;

    let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
        isPredicated = 1 in {
      defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
      defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
    }
  }
}

let addrMode = BaseImmOffset in {
  defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
                               11, 6>, AddrModeRel;
  defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
                                11, 6>, AddrModeRel;
  defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
                               12, 7>, AddrModeRel;
  defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
                                12, 7>, AddrModeRel;
  defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
                               13, 8>, AddrModeRel;
  defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
                               14, 9>, AddrModeRel;
}

let AddedComplexity = 20 in {
def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
            (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;

def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
            (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;

def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
            (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;

def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
            (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;

def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
            (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;

def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
            (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
}

let neverHasSideEffects = 1 in
def LDrid_GP : LDInst2<(outs DoubleRegs:$dst),
            (ins globaladdress:$global, u16Imm:$offset),
            "$dst = memd(#$global+$offset)",
            []>,
            Requires<[NoV4T]>;

let neverHasSideEffects = 1, validSubTargets = NoV4SubT in
def LDd_GP : LDInst2<(outs DoubleRegs:$dst),
            (ins globaladdress:$global),
            "$dst = memd(#$global)",
            []>,
            Requires<[NoV4T]>;

//===----------------------------------------------------------------------===//