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  • Vikram S. Adve's avatar
    (1) Added special register class containing (for now) %fsr. · 7366fa1a
    Vikram S. Adve authored 
        Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341
    7366fa1a