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    Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE · 8c2d062e
    Evan Cheng authored
    instructions.
    
    e.g.
    %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
    %reg1027<def> = EXTRACT_SUBREG %reg1026, 6
    %reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
    ...
    %reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
    
    After REG_SEQUENCE is eliminated, we are left with:
    
    %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
    %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
    %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
    
    The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
    know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
    target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
    sub-register (or combined to be reg1026 itself as is the case here). If it is possible, 
    it will be able to replace references of reg1026 with reg1029 + the larger sub-register
    index.
    
    llvm-svn: 103835
    8c2d062e
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