Before register allocation, instructions can be moved across calls in
order to reduce register pressure.  After register allocation, we don't
gain a lot by moving callee-saved defs across calls.  In fact, since the
scheduler doesn't have a good idea how registers are used in the callee,
it can't really make good scheduling decisions.

This changes the schedule in two ways: 1. Latencies to call uses and
defs are no longer accounted for, causing some random shuffling around
calls.  This isn't really a problem since those uses and defs are
inaccurate proxies for what happens inside the callee.  They don't
represent registers used by the call instruction itself.

2. Instructions are no longer moved across calls.  This didn't happen
very often, and the scheduling decision was made on dubious information
anyway.

As with any scheduling change, benchmark numbers shift around a bit,
but there is no positive or negative trend from this change.

This makes the post-ra scheduler 5% faster for ARM targets.

The secret motivation for this patch is the introduction of register
mask operands representing call clobbers.  The most efficient way of
handling regmasks in ScheduleDAGInstrs is to model them as barriers for
physreg live ranges, but not for virtreg live ranges.  That's fine
pre-ra, but post-ra it would have the same effect as this patch.

llvm-svn: 151265