llvm/lib/Target/Mips/Mips64InstrInfo.td · cf7e5b0976f2b03a4317f52291f11e560eb58bbc · Roger Ferrer / llvm-epi-0.8 · GitLab

This is an archived project. Repository and other project resources are read-only.

Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted · cf7e5b09
Akira Hatanaka authored Nov 07, 2011
```
when shift amount is larger than 32.

llvm-svn: 143990
```
cf7e5b09