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  • Jakob Stoklund Olesen's avatar
    Allow a register to be redefined multiple times in a basic block. · 207cd4bb
    Jakob Stoklund Olesen authored
    LiveVariableAnalysis was a bit picky about a register only being redefined once,
    but that really isn't necessary.
    
    Here is an example of chained INSERT_SUBREGs that we can handle now:
    
    68      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14
                    register: %reg1040 +[70,134:0)
    76      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13
                    register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0)  0@78-(134) 1@70-(78)
    84      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12
                    register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0)  0@86-(134) 1@70-(78) 2@78-(86)
    92      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11
                    register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0)  0@94-(134) 1@70-(78) 2@78-(86) 3@86-(94)
    
    rdar://problem/8096390
    
    llvm-svn: 106152
    207cd4bb
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