llvm/include/llvm/Target/TargetInstrInfo.h

llvm/include/llvm/Target/TargetRegisterInfo.h

llvm/lib/CodeGen/PostRASchedulerList.cpp

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp

llvm/lib/Target/ARM/ARMInstrInfo.cpp

llvm/lib/Target/ARM/ARMInstrInfo.h

llvm/lib/Target/ARM/ARMRegisterInfo.cpp

llvm/lib/Target/ARM/ARMRegisterInfo.h

llvm/lib/Target/CellSPU/SPUInstrInfo.cpp

llvm/lib/Target/CellSPU/SPUInstrInfo.h

llvm/lib/Target/CellSPU/SPURegisterInfo.cpp

llvm/lib/Target/CellSPU/SPURegisterInfo.h

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

llvm/lib/Target/PowerPC/PPCInstrInfo.h

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

llvm/lib/Target/PowerPC/PPCRegisterInfo.h

llvm/lib/Target/X86/X86InstrInfo.cpp

llvm/lib/Target/X86/X86InstrInfo.h

llvm/lib/Target/X86/X86RegisterInfo.cpp

llvm/lib/Target/X86/X86RegisterInfo.h