[RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero

c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C.
This patch adds uimmlog2xlennonzero to reflect this constraint as well as
tests.

Differential Revision: https://reviews.llvm.org/D41216

Patch by Shiva Chen.

llvm-svn: 320799