"The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), but

the Intel manual (screenshot) says it should be 0b11110110 (f6).  The existing
encoding causes a disassembly conflict with MMX_PAVGBrm, which really should be
0f e0."

Patch by Sean Callanan!

llvm-svn: 72508